JPS6359184B2 - - Google Patents
Info
- Publication number
- JPS6359184B2 JPS6359184B2 JP56196858A JP19685881A JPS6359184B2 JP S6359184 B2 JPS6359184 B2 JP S6359184B2 JP 56196858 A JP56196858 A JP 56196858A JP 19685881 A JP19685881 A JP 19685881A JP S6359184 B2 JPS6359184 B2 JP S6359184B2
- Authority
- JP
- Japan
- Prior art keywords
- arithmetic processing
- cpu
- transmission means
- processing device
- information transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
- G06F11/1691—Temporal synchronisation or re-synchronisation of redundant processing components using a quantum
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56196858A JPS5899866A (ja) | 1981-12-09 | 1981-12-09 | 2重化演算処理システム |
| DE8282111353T DE3279941D1 (en) | 1981-12-09 | 1982-12-08 | Multi-computer system |
| EP82111353A EP0081238B1 (en) | 1981-12-09 | 1982-12-08 | Multi-computer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56196858A JPS5899866A (ja) | 1981-12-09 | 1981-12-09 | 2重化演算処理システム |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5899866A JPS5899866A (ja) | 1983-06-14 |
| JPS6359184B2 true JPS6359184B2 (enrdf_load_stackoverflow) | 1988-11-18 |
Family
ID=16364822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56196858A Granted JPS5899866A (ja) | 1981-12-09 | 1981-12-09 | 2重化演算処理システム |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5899866A (enrdf_load_stackoverflow) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53100743A (en) * | 1977-02-15 | 1978-09-02 | Agency Of Ind Science & Technol | Synchronous processor between processors |
| JPS6024981B2 (ja) * | 1977-06-01 | 1985-06-15 | 株式会社日立製作所 | デ−タ転送システム |
| JPS599999B2 (ja) * | 1978-08-15 | 1984-03-06 | 日本電信電話株式会社 | 同期運転方式 |
| JPS5599630A (en) * | 1979-01-25 | 1980-07-29 | Toshiba Corp | Time correction method |
-
1981
- 1981-12-09 JP JP56196858A patent/JPS5899866A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5899866A (ja) | 1983-06-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0306211A3 (en) | Synchronized twin computer system | |
| JPS6359184B2 (enrdf_load_stackoverflow) | ||
| US6023768A (en) | Phase locked distributed time reference for digital processing and method therefor | |
| JPS6246028B2 (enrdf_load_stackoverflow) | ||
| JPS648380B2 (enrdf_load_stackoverflow) | ||
| JPS59127164A (ja) | マルチシステムの同期化装置 | |
| EP0286235A2 (en) | Automatic determination of the number of processor modules for multiprocessor systems | |
| KR102819281B1 (ko) | 이종 시스템 간 동기화 장치 및 방법 | |
| SU1221656A1 (ru) | Многоканальное устройство управлени обменом информацией между ЭВМ | |
| JPH0586582B2 (enrdf_load_stackoverflow) | ||
| JP2703277B2 (ja) | データプロセツサの同期回路装置 | |
| JPH01145758A (ja) | 多重系計算機システムの時刻同期方式 | |
| JPS6384228A (ja) | クロック同期データ伝送方式 | |
| CN109194334A (zh) | 一种应用于多通道高速数模转换器的同步系统 | |
| JPH0126096B2 (enrdf_load_stackoverflow) | ||
| KR930004948B1 (ko) | 마이컴간 데이타 통신방법 | |
| KR100206359B1 (ko) | 브이엠이 버스시스템으로 구축한 비디오 트리거보드 | |
| JPH0395660A (ja) | 複数中央処理装置システムにおけるシステム時刻設定方式 | |
| SU1405065A1 (ru) | Устройство дл сопр жени двух магистралей | |
| JPS61204757A (ja) | プロセツサ間通信方式 | |
| JPH02270010A (ja) | 多重系計算機システムの時刻同期方法 | |
| JPS6337420B2 (enrdf_load_stackoverflow) | ||
| JPH0156416B2 (enrdf_load_stackoverflow) | ||
| JPS59188257A (ja) | 信号伝送方式 | |
| JPH01218145A (ja) | 多重アクセス制御方式 |