JPS6357745U - - Google Patents

Info

Publication number
JPS6357745U
JPS6357745U JP15101186U JP15101186U JPS6357745U JP S6357745 U JPS6357745 U JP S6357745U JP 15101186 U JP15101186 U JP 15101186U JP 15101186 U JP15101186 U JP 15101186U JP S6357745 U JPS6357745 U JP S6357745U
Authority
JP
Japan
Prior art keywords
probe
card
probe card
needles
rows
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15101186U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15101186U priority Critical patent/JPS6357745U/ja
Publication of JPS6357745U publication Critical patent/JPS6357745U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Measuring Leads Or Probes (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の一実施例を縦断面で切断し
た状態で示す斜視図、第2図および第3図は第1
図に示すプローブ針3,4の配置を示すための模
式的な平面図であり、それぞれボンデイング・パ
ツト5,6が2重に配置されている場合と、千鳥
状に配置されている場合である。 1…第1のプローブ・カード、2…第2のプロ
ーブ・カード、3,4…プローブ針、5…内側ボ
ンデイング・パツト、6…外側ボンデイング・パ
ツト、7…チツプ、8…テスター接続端子、9…
絶縁緩衝材。
FIG. 1 is a perspective view showing one embodiment of the present invention cut in longitudinal section, and FIGS.
FIG. 4 is a schematic plan view showing the arrangement of the probe needles 3 and 4 shown in the figure, in which the bonding pads 5 and 6 are arranged in a double manner and in a staggered manner, respectively. . DESCRIPTION OF SYMBOLS 1...First probe card, 2...Second probe card, 3, 4...Probe needle, 5...Inner bonding pad, 6...Outer bonding pad, 7...Tip, 8...Tester connection terminal, 9 …
Insulated cushioning material.

Claims (1)

【実用新案登録請求の範囲】 (1) 半導体集積回路チツプの周辺に2列に並べ
られたパツトに対応してプローブ針を2列に並べ
て設けたことを特徴とするプローブ・カード。 (2) それぞれがプローブ針を1列に並べた第1
および第2のプローブ・カードを有し、この第1
および第2のプローブ・カードが脱着可能である
実用新案登録請求の範囲第1項記載のプローブ・
カード。
[Claims for Utility Model Registration] (1) A probe card characterized in that probe needles are arranged in two rows corresponding to the parts arranged in two rows around a semiconductor integrated circuit chip. (2) Each has a first line of probe needles arranged in a row.
and a second probe card;
and the probe according to claim 1, wherein the second probe card is removable.
card.
JP15101186U 1986-09-30 1986-09-30 Pending JPS6357745U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15101186U JPS6357745U (en) 1986-09-30 1986-09-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15101186U JPS6357745U (en) 1986-09-30 1986-09-30

Publications (1)

Publication Number Publication Date
JPS6357745U true JPS6357745U (en) 1988-04-18

Family

ID=31067679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15101186U Pending JPS6357745U (en) 1986-09-30 1986-09-30

Country Status (1)

Country Link
JP (1) JPS6357745U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002082528A1 (en) * 2001-04-04 2002-10-17 Fujitsu Limited Contactor device for semiconductor device and method of testing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002082528A1 (en) * 2001-04-04 2002-10-17 Fujitsu Limited Contactor device for semiconductor device and method of testing semiconductor device

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