JPS63152243U - - Google Patents
Info
- Publication number
- JPS63152243U JPS63152243U JP4374987U JP4374987U JPS63152243U JP S63152243 U JPS63152243 U JP S63152243U JP 4374987 U JP4374987 U JP 4374987U JP 4374987 U JP4374987 U JP 4374987U JP S63152243 U JPS63152243 U JP S63152243U
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- protrusion
- probe card
- insulating substrate
- flexible insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000523 sample Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 238000003384 imaging method Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Measuring Leads Or Probes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
第１図は、この考案に係るプローブカードの一
実施例を示す平面図、第２図は、その要部断面図
、第３図は、この考案に係るプローブカードの他
の一実施例を示す平面図、第４図は、この考案に
係るプローブカードが装填される半導体ウエハプ
ローバの一実施例を示す主要部の概略側面図であ
る。
１…フレキシブル絶縁基板、２…配線パターン
、３…コンタクト、４…スルーホール、ＢＳ…ベ
ース、ＸＳ…Ｘステージ、ＹＳ…Ｙステージ、Ｚ
…Ｚステージ、θ…θステージ、ＷＦ…半導体ウ
エハ、ＩＴＶ１，ｌＴＶ２…撮像装置、ＦＰ…プ
ローブカード、ＰＨ…プローブカードホルダー、
ＨＦＴＨ…高周波テストヘツド。
FIG. 1 is a plan view showing one embodiment of the probe card according to this invention, FIG. 2 is a sectional view of the main part thereof, and FIG. 3 is a plan view showing another embodiment of the probe card according to this invention. The plan view and FIG. 4 are schematic side views of the main parts of an embodiment of a semiconductor wafer prober loaded with a probe card according to the present invention. 1...Flexible insulating substrate, 2...Wiring pattern, 3...Contact, 4...Through hole, BS...Base, XS...X stage, YS...Y stage, Z
...Z stage, θ...θ stage, WF...semiconductor wafer, ITV1, lTV2...imaging device, FP...probe card, PH...probe card holder,
HFTH...High frequency test head.
Claims (1)
一端が半導体ウエハ上に形成される半導体チツプ
に設けられるパツドに対応して延びるとともにハ
ーフエツチングにより突起を持つようにされた配
線パターンを含み、上記一端の突起部を上記半導
体チツプのパツドに対する接触電極としたことを
特徴とするプローブカード。 ２ 上記配線パターンは、フレキシブルな絶縁基
板の両面に形成され、一方の面に形成される配線
パターンの一端はそのまま上記突起部が設けられ
、他方の面に形成される配線パターンはスルーホ
ールを介して上記一方の面に突起部を持つよう形
成された配線パターンに接続されるものであるこ
とを特徴とする実用新案登録請求の範囲第１項記
載のプローブカード。[Claims for Utility Model Registration] 1. Formed on a flexible insulating substrate, one end of which extends to correspond to a pad provided on a semiconductor chip formed on a semiconductor wafer, and is half-etched to have a protrusion. 1. A probe card comprising a wiring pattern, the protrusion at one end serving as a contact electrode for a pad of the semiconductor chip. 2 The above wiring pattern is formed on both sides of a flexible insulating substrate, one end of the wiring pattern formed on one side is directly provided with the above protrusion, and the wiring pattern formed on the other side is formed through a through hole. 2. The probe card according to claim 1, wherein the probe card is connected to a wiring pattern formed to have a protrusion on one surface thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4374987U JPS63152243U (en) | 1987-03-25 | 1987-03-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4374987U JPS63152243U (en) | 1987-03-25 | 1987-03-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63152243U true JPS63152243U (en) | 1988-10-06 |
Family
ID=30860905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4374987U Pending JPS63152243U (en) | 1987-03-25 | 1987-03-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63152243U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000200812A (en) * | 1990-02-16 | 2000-07-18 | Glenn J Leedy | Manufacture and test method for integrated circuit using high density probe point |
-
1987
- 1987-03-25 JP JP4374987U patent/JPS63152243U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000200812A (en) * | 1990-02-16 | 2000-07-18 | Glenn J Leedy | Manufacture and test method for integrated circuit using high density probe point |
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