JPH02146441U - - Google Patents

Info

Publication number
JPH02146441U
JPH02146441U JP5675389U JP5675389U JPH02146441U JP H02146441 U JPH02146441 U JP H02146441U JP 5675389 U JP5675389 U JP 5675389U JP 5675389 U JP5675389 U JP 5675389U JP H02146441 U JPH02146441 U JP H02146441U
Authority
JP
Japan
Prior art keywords
group
electrodes
same
inputs
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5675389U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5675389U priority Critical patent/JPH02146441U/ja
Publication of JPH02146441U publication Critical patent/JPH02146441U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの考案の一実施例であるグルーピン
グされた１つのグループにプロービングした状態
の平面図、第２図は第１図のＩＣチツプを移動さ
せて他のグループにプロービングした状態の平面
図、第３図は従来のＩＣチツプにプロービングし
た状態を示す平面図である。 １はＩＣチツプ、２は電極、２ａはグルーピン
グした１グループの電極、２ｂはグルーピングし
た他のグループの電極、３ａはこの考案の１つの
グループのテスト用プローブ針も示す。なお、図
中、同一符号は同一、または相当部分を示す。 Fig. 1 is a plan view of an embodiment of this invention in which one group is probed, and Fig. 2 is a plan view of the IC chip in Fig. 1 moved and probed into another group. , FIG. 3 is a plan view showing a state in which a conventional IC chip is probed. 1 is an IC chip, 2 is an electrode, 2a is one group of electrodes, 2b is another group of electrodes, and 3a is a test probe needle of one group of this invention. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入出力を機能別に複数のグループに分けた半導
体集積回路において、各グループ間で電極の相対
的配置を等しくしたことを特徴とする半導体集積
回路。 1. A semiconductor integrated circuit in which inputs and outputs are divided into a plurality of groups according to function, characterized in that the relative arrangement of electrodes is the same between each group.
JP5675389U 1989-05-17 1989-05-17 Pending JPH02146441U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5675389U JPH02146441U (en) 1989-05-17 1989-05-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5675389U JPH02146441U (en) 1989-05-17 1989-05-17

Publications (1)

Publication Number Publication Date
JPH02146441U true JPH02146441U (en) 1990-12-12

Family

ID=31580860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5675389U Pending JPH02146441U (en) 1989-05-17 1989-05-17

Country Status (1)

Country Link
JP (1) JPH02146441U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010153877A (en) * 2010-01-08 2010-07-08 Fujitsu Semiconductor Ltd Semiconductor chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010153877A (en) * 2010-01-08 2010-07-08 Fujitsu Semiconductor Ltd Semiconductor chip

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