JPS6351378B2 - - Google Patents

Info

Publication number
JPS6351378B2
JPS6351378B2 JP55134224A JP13422480A JPS6351378B2 JP S6351378 B2 JPS6351378 B2 JP S6351378B2 JP 55134224 A JP55134224 A JP 55134224A JP 13422480 A JP13422480 A JP 13422480A JP S6351378 B2 JPS6351378 B2 JP S6351378B2
Authority
JP
Japan
Prior art keywords
substrate
semiconductor substrate
semiconductor
holding
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55134224A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5759349A (en
Inventor
Haruo Mori
Yasuo Oono
Yutaka Oota
Hiroshi Tanabe
Kotaro Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP55134224A priority Critical patent/JPS5759349A/ja
Priority to US06/302,351 priority patent/US4530001A/en
Publication of JPS5759349A publication Critical patent/JPS5759349A/ja
Publication of JPS6351378B2 publication Critical patent/JPS6351378B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Landscapes

  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
JP55134224A 1980-09-29 1980-09-29 Manufacture of semiconductor device Granted JPS5759349A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP55134224A JPS5759349A (en) 1980-09-29 1980-09-29 Manufacture of semiconductor device
US06/302,351 US4530001A (en) 1980-09-29 1981-09-15 High voltage integrated semiconductor devices using a thermoplastic resin layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55134224A JPS5759349A (en) 1980-09-29 1980-09-29 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5759349A JPS5759349A (en) 1982-04-09
JPS6351378B2 true JPS6351378B2 (enExample) 1988-10-13

Family

ID=15123316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55134224A Granted JPS5759349A (en) 1980-09-29 1980-09-29 Manufacture of semiconductor device

Country Status (2)

Country Link
US (1) US4530001A (enExample)
JP (1) JPS5759349A (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4866501A (en) * 1985-12-16 1989-09-12 American Telephone And Telegraph Company At&T Bell Laboratories Wafer scale integration
US4793883A (en) * 1986-07-14 1988-12-27 National Starch And Chemical Corporation Method of bonding a semiconductor chip to a substrate
US5191224A (en) * 1987-04-22 1993-03-02 Hitachi, Ltd. Wafer scale of full wafer memory system, packaging method thereof, and wafer processing method employed therein
GB2206445A (en) * 1987-07-01 1989-01-05 Spectrol Reliance Ltd Method of manufacturing dielectrically isolated integrated circuits and circuit elements
JPS6437492U (enExample) * 1987-08-31 1989-03-07
US4904610A (en) * 1988-01-27 1990-02-27 General Instrument Corporation Wafer level process for fabricating passivated semiconductor devices
JP3034528B2 (ja) * 1988-04-06 2000-04-17 ソニー株式会社 半導体装置の製造方法
US4918505A (en) * 1988-07-19 1990-04-17 Tektronix, Inc. Method of treating an integrated circuit to provide a temperature sensor that is integral therewith
US4871921A (en) * 1988-08-09 1989-10-03 Honeywell Inc. Detector array assembly having bonding means joining first and second surfaces except where detectors are disposed
US6262434B1 (en) 1996-08-23 2001-07-17 California Micro Devices Corporation Integrated circuit structures and methods to facilitate accurate measurement of the IC devices
FR2782840B1 (fr) * 1998-08-25 2003-09-05 Commissariat Energie Atomique Circuit electronique et procede de realisation d'un circuit electronique integre comprenant au moins un composant electronique de puissance dans une plaque de substrat
KR20010102310A (ko) * 1999-12-24 2001-11-15 롤페스 요하네스 게라투스 알베르투스 매립된 절연층상에 위치한 실리콘 웨이퍼의 상부층에형성된 반도체 소자를 포함하는 반도체 장치의 제조방법

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3475664A (en) * 1965-06-30 1969-10-28 Texas Instruments Inc Ambient atmosphere isolated semiconductor devices
US3416224A (en) * 1966-03-08 1968-12-17 Ibm Integrated semiconductor devices and fabrication methods therefor
US4296428A (en) * 1979-06-28 1981-10-20 Rockwell International Corporation Merged field effect transistor circuit and fabrication process

Also Published As

Publication number Publication date
JPS5759349A (en) 1982-04-09
US4530001A (en) 1985-07-16

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