JPS6338327U - - Google Patents

Info

Publication number
JPS6338327U
JPS6338327U JP12947586U JP12947586U JPS6338327U JP S6338327 U JPS6338327 U JP S6338327U JP 12947586 U JP12947586 U JP 12947586U JP 12947586 U JP12947586 U JP 12947586U JP S6338327 U JPS6338327 U JP S6338327U
Authority
JP
Japan
Prior art keywords
film
semiconductor device
bonding pad
film thickness
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12947586U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12947586U priority Critical patent/JPS6338327U/ja
Publication of JPS6338327U publication Critical patent/JPS6338327U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • H01L2224/05557Shape in side view comprising protrusions or indentations

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す断面図、第2
図と第3図は夫々本考案の他の実施例を示す断面
図、第4図は従来構造の半導体装置アルミニウム
パツド部の構成を示す断面図、第5図は他の従来
のパツド構造を示す断面図、第6図はアルミニウ
ムパツド中に生じるSi柱の説明図である。 1……半導体基板、2……フイルド酸化膜、3
……PSG膜、4……アルミニウムパツド、4―
a……アルミニウムパツド中のSi柱(粒)、4
1……純アルミニウム膜、42……アルミニウム
パツド膜、43……純アルミニウムの緩衝膜、5
……パツシベーシヨン膜、6……保護膜。
Fig. 1 is a sectional view showing one embodiment of the present invention;
3 and 3 are cross-sectional views showing other embodiments of the present invention, FIG. 4 is a cross-sectional view showing the configuration of an aluminum pad portion of a semiconductor device having a conventional structure, and FIG. 5 is a cross-sectional view showing another conventional pad structure. The cross-sectional view shown in FIG. 6 is an explanatory diagram of Si pillars generated in the aluminum pad. 1...Semiconductor substrate, 2...Field oxide film, 3
...PSG film, 4...Aluminum pad, 4-
a... Si pillar (grain) in aluminum pad, 4
1... Pure aluminum film, 42... Aluminum pad film, 43... Pure aluminum buffer film, 5
...passivation film, 6...protective film.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体基板上にフイルド酸化膜、PSG膜等を
介して外部リードとの接続のため設けるボンデイ
ングパツドを有する半導体装置において、前記ボ
ンデイングパツドをSiを含有するアルミニウム
層で構成し、パツドあるいはパツドにおいてのボ
ンデイングに必要な領域の膜厚を配線層等の膜厚
に比較して十分薄くしたことを特徴とする半導体
装置。
In a semiconductor device having a bonding pad provided on a semiconductor substrate for connection with an external lead via a field oxide film, a PSG film, etc., the bonding pad is composed of an aluminum layer containing Si, and 1. A semiconductor device characterized in that a film thickness in a region required for bonding is sufficiently thin compared to a film thickness of a wiring layer, etc.
JP12947586U 1986-08-27 1986-08-27 Pending JPS6338327U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12947586U JPS6338327U (en) 1986-08-27 1986-08-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12947586U JPS6338327U (en) 1986-08-27 1986-08-27

Publications (1)

Publication Number Publication Date
JPS6338327U true JPS6338327U (en) 1988-03-11

Family

ID=31026076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12947586U Pending JPS6338327U (en) 1986-08-27 1986-08-27

Country Status (1)

Country Link
JP (1) JPS6338327U (en)

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