JPS6127348U - bonding pad electrode - Google Patents

bonding pad electrode

Info

Publication number
JPS6127348U
JPS6127348U JP1984110469U JP11046984U JPS6127348U JP S6127348 U JPS6127348 U JP S6127348U JP 1984110469 U JP1984110469 U JP 1984110469U JP 11046984 U JP11046984 U JP 11046984U JP S6127348 U JPS6127348 U JP S6127348U
Authority
JP
Japan
Prior art keywords
bonding pad
pad electrode
semiconductor layer
plan
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984110469U
Other languages
Japanese (ja)
Inventor
幸也 田中
三樹 阿部
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP1984110469U priority Critical patent/JPS6127348U/en
Publication of JPS6127348U publication Critical patent/JPS6127348U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05096—Uniform arrangement, i.e. array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１Ａ図及び第１Ｂ図はそれぞれ本考案に係るボンデイ
ングパッド電極の第１実施例を示す平面図及びそのＩ−
Ｉ線の断面図、第２Ａ図及び第２Ｂ図はそれぞれ第１実
坤例において腐食によりん膜の欠損が生じた後の状態を
示す第ＩＡ図及ひ第ＩＢ図と同様な平面図及びその■−
■線の断面図、第３Ａ図及び第３Ｂ図はそれぞれ本考案
に係るボンデイングパッド電極の第２実施例を示す平面
図及びその■−■線の断面図、第４Ａ図及び第４Ｂ図は
それぞれ本考案に係るボンデイングパッド電極の第３実
施例を示す平面図及びその■一■線の断面図、第５図は
従来のボンデイングパツド電極を示す平面図、第６図は
第５図において腐食によりボンデイングパッド電極の欠
損が生じた・後の状態を示す第２Ａ図と同様な平面図で
ある。 なお図面に用いた符号において、１・・・パツシベーシ
ョン膜、２・・・ボンデイングパツド電極、３・・・ワ
イヤー、５・・・シリコン基板、７・・・多結晶シリコ
ン膜（半導体層）、９・・・ＡＩ膜（金属膜）、であ一 ク●1A and 1B are a plan view showing a first embodiment of a bonding pad electrode according to the present invention, and FIG.
The cross-sectional view taken along line I, FIGS. 2A and 2B are a plan view similar to FIGS. ■−
3A and 3B are a plan view showing the second embodiment of the bonding pad electrode according to the present invention, and a sectional view taken along the line 2 and 4A and 4B, respectively. A plan view showing a third embodiment of the bonding pad electrode according to the present invention and a cross-sectional view taken along the line 1-2 of the same, FIG. 5 is a plan view showing a conventional bonding pad electrode, and FIG. FIG. 2A is a plan view similar to FIG. 2A, showing a state after the bonding pad electrode is damaged due to the above-mentioned problems. In addition, in the symbols used in the drawings, 1... Passivation film, 2... Bonding pad electrode, 3... Wire, 5... Silicon substrate, 7... Polycrystalline silicon film (semiconductor layer). ), 9...AI film (metal film), one click ●

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体層と、この半導体層上に設けられている金属膜と
をそれぞれ具備することを特徴とするボンデイングパッ
ド電極。A bonding pad electrode comprising a semiconductor layer and a metal film provided on the semiconductor layer.
JP1984110469U 1984-07-21 1984-07-21 bonding pad electrode Pending JPS6127348U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984110469U JPS6127348U (en) 1984-07-21 1984-07-21 bonding pad electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984110469U JPS6127348U (en) 1984-07-21 1984-07-21 bonding pad electrode

Publications (1)

Publication Number Publication Date
JPS6127348U true JPS6127348U (en) 1986-02-18

Family

ID=30669597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984110469U Pending JPS6127348U (en) 1984-07-21 1984-07-21 bonding pad electrode

Country Status (1)

Country Link
JP (1) JPS6127348U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0377794U (en) * 1989-11-30 1991-08-06
JPH0454787U (en) * 1990-09-14 1992-05-11

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0377794U (en) * 1989-11-30 1991-08-06
JPH0454787U (en) * 1990-09-14 1992-05-11

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