JPS6334974A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive accomplishment of a high degree of integration as well as to increase the capacitance of an MIM capacitor by a method wherein a metal-insulator-metal (MIM) capacitor is formed in the first hole recessed part formed in a semiconductor substrate. CONSTITUTION:In the recessed part and the opening part of the first hole 1a, the first metal layer 2, the three-layers consisting of an insulative layer 3, the third metal layer 222, form a threedimensional MIM structure, and as the first metal layer 2 has the junction part with the second metal layer 22, the earthing to the rear side of a GaAs substrate 1 is accomplished. As the area of the electrode of an MIM capacitor depends upon the surface area of the recessed part of the first hole 1a, namely, the amount of etching of the first hole 1a, the capacitance of the MIM capacitor can be controlled by regulating the amount of etching of the first hole 1a. As a result, the occupation area of the via-hole and the MIM capacitor on the circuit chip can be held small, a high degree of integration of circuit can be accomplished, and the MIM capacitor having a large volume can be formed in a limited space.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor devices, and particularly relates to via holes and M
The present invention relates to a semiconductor integrated circuit having an IM capacitor.

[Conventional technology]

FIGS. 2 and 3 are cross-sectional views of main parts showing an example of the structure of a conventional semiconductor device, and the conventional semiconductor device will be explained below using these figures.

In FIGS. 2 and 3, 1 is a GaAs substrate;
1a is the first hole, lbf is the second hole, 2(, f is the first hole
22 is a second metal layer, 222 is a third metal layer, and 3 is an insulator layer. However, the first hole 1
The name a is defined as a hole formed from the front side of the GaAs substrate 1, and the second hole 1b is defined as a hole formed from the back side of the GaAs substrate 1.

In the conventional semiconductor device shown in FIG. 2, via holes (holes penetrating from the front surface to the back surface of the GaAs substrate 1) are formed in the GaAs substrate 1, and include a first hole 1a, a second hole lb, and a second hole lb. A first metal layer 2 formed in those recesses. It is composed of a second metal layer 22. The first metal layer 2.t is located adjacent to the opening 1'' of the first hole 1a. Insulator layer 3. M I M composed of the third metal part 222
(Kinman-insulator-metal structure) A carrier bank is arranged.

On the other hand, the conventional semiconductor device shown in FIG. 3 has an MIM cavity (consisting of a first metal layer 2, an insulator layer 3, and a third metal layer 222) that covers the via hole A. By arranging the
It consists of a second hole 1b formed by etching from the back side of the substrate 1 and a second metal layer 22 formed in the recessed portion thereof.

FIG. 4 shows an equivalent circuit of the semiconductor device shown in FIGS. 2 and 3. In FIG. 4, 4 indicates a capacitor and 5 indicates a grounding portion, the via hole corresponds to the grounding portion 5, and the MIM capacitor corresponds to the capacitor 4.

[Problems to be Solved by the Invention] In a conventional semiconductor device as shown in FIG. 2, in an integrated circuit chip formed on a compound semiconductor substrate such as a GaAs substrate 1, metal pads (second
In the figure, the first metal layer 2) and the MIM capacitor occupy a large area, which is disadvantageous for high integration of the circuit. In addition, since the structure of the MIM capacitor is planar, the area that can be used as the space for the electrode of capacitor 4 on the circuit is easily subject to design restrictions, and
There was a problem in that it was also disadvantageous for increasing the capacity.

On the other hand, the via hole (second hole 1b) in the conventional semiconductor device shown in FIG. It is formed of.

According to wet etching, which is normally used for etching via holes, the side edge jig is large, and the etching progresses almost isotropically, resulting in a finish that is different from that of the via hole in the semiconductor device format shown in Figure 2. The width is almost twice as large (see Japanese Patent Laid-Open No. 60-7440). When using the above wet etching method, forming a MIM capacitor on the via hole and evaluating the strength of the circuit chip, when looking at the circuit chip from above, the MIM capacitor is The area of the metal pad (first metal layer 2) which is to become the ground-side electrode of the GaAs substrate must be at least as large as the area of the opening of the second hole 1b on the back surface of the GaAs substrate. It is still disadvantageous. Further, since the structure of the MIM cabassic is planar, there is a problem in that it is disadvantageous in increasing the capacitance of the capacitor 3, similar to the conventional semiconductor device shown in FIG.

The present invention was made in order to solve the above-mentioned problems, and aims to provide a semiconductor device that allows for highly integrated circuits and a large capacity MIM capacitor.

[Means for solving problems]

A semiconductor device according to the present invention has an MIM carrier bank formed in a first hole recess formed in a semiconductor substrate.

[Effect]

In this invention, since the MfM cavity is formed in the first hole recess, the area occupied by the via hole and the MIM capacitor on the circuit chip can be kept small, the MIM cavity can be made into a three-dimensional structure, and the MfM cavity can be formed in a three-dimensional structure.
Make the electrode area of the M capacitor large even within the limited space.

〔Example〕

FIG. 1 is a cross-sectional view of the main parts of a semiconductor device showing an embodiment of the present invention, and FIG.

The same reference numerals as in FIG. 3 indicate the same components.

In FIG. 1, in the recess and opening of the first hole 1a, the first metal layer 2. Insulator layer 3. Third metal layer 222
The three layers form a three-dimensional MIM structure, and the first metal layer 2 has a joint portion with the second metal layer 22, so that it is grounded to the back side of the GaAs substrate 1. Therefore, the equivalent circuit of the semiconductor device according to the present invention shown in FIG. 1 is as shown in FIG. 4, similar to the equivalent circuit of the conventional semiconductor device shown in FIGS. 2 and 3. In addition,
Since the area (surface area) of the electrode of the MIM capacitor depends on the surface area of the concave portion of the first ball 1a, that is, the amount of etching of the first hole 1a, the capacitance of the MIM capacitor is adjusted by the amount of etching and re-sizing of the first hole ia. You can control it by doing what you do.

〔Effect of the invention〕

As explained above, this invention forms an MIM carrier bank in the four parts of the first hole formed in a semiconductor substrate, so that it is possible to highly integrate a semiconductor device, and to obtain a large capacity M[M] in a limited space. This has the effect of forming a cavanck.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the main parts of a semiconductor device showing an embodiment of the present invention, FIGS. 2 and 3 are cross-sectional views of the main parts showing an example of the structure of a conventional semiconductor device, and FIG. FIG. 4 is an equivalent circuit diagram of the semiconductor device shown in FIGS. 1 to 3. FIG. In the figure, 1 is a GaAs substrate, 1a is a first hole,
, lb is the second hole, 2 is the first metal layer, 3 is the insulating layer, 2
2 is a second metal layer, and 222 is a third metal layer. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 3 2-2 Figure 4 1/4 - Jail' Voluntary to write amendments to the procedure) 1. Indication of the incident: Patent Application No. 179516/1986 2,
Title of the invention: Semiconductor device 3, relationship to the amended case Patent applicant address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo. Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent Address 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo
, Column 2 of Detailed Description of the Invention of the Specification Subject to Amendment 2 Column of Brief Description of Drawings and Drawing 6 Contents of Amendment (1) [Condenser 3-1] on page 5, line 6 of the specification
[Correct with capacitor 4-1. (2) Also on page 7, lines 15-16, “3 is the insulating layer i.
is corrected as [3: insulator layer I]. (3) Revise Figures 1 and 3 as shown in the attached sheet. that's all

Claims (1)

[Claims] 1 of the thickness of the compound semiconductor substrate from the surface of the compound semiconductor substrate
A first hole with a depth of about A MIM capacitor is formed by three metal layers, and a second hole is formed from the back surface of the compound semiconductor substrate so as to be axially aligned with the drilling position of the first hole and have a penetrating portion with the first hole. A semiconductor device characterized in that a second metal layer is formed in the recessed portion of the semiconductor device so as to have a contact portion with at least a portion of the first metal layer.