JPH0425172A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the backing wiring of a word line which is lessened in wiring resistance to operate at a high speed by a method wherein the backing wirings adjacent to each other are formed of different layers. CONSTITUTION:Concerning the backing wiring of a word line of a MOS DRAM (dynamic random access memory), a word line 1, a bit line 2, capacitors 3 and 8, and a backing wiring 4 are provided onto a semiconductor substrate. The backing wiring 4 is connected to the word line 1 in parallel, and adjacent backing wirings 4A and 4B are formed of different layers and stacked up through the intermediary of an insulating film 9. That is, the adjacent backing wirings 4A and 4B distant from each other by a very small space are formed of different layers. By this setup, a wiring can be formed wider extending to surplus regions in the layers to lessen in wiring resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to word line backing wiring of a MOS DRAM (dynamic random access memory).

The purpose is to provide word line backing wiring that enables miniaturization and higher reliability of MOS DRAM, reduces wiring resistance, and increases speed.

A word line (1), a bit line (2), a capacitor (3L (8)) and a backing wiring (8) are formed on a semiconductor substrate.
4), the backing wiring (
4) is connected in parallel to the word line (1), and adjacent backing wirings (4A) and (4B) are formed in different layers, and are configured to overlap with each other with an insulating film interposed therebetween.

[Industrial application field]

The present invention relates to a semiconductor device, and more particularly to backing wiring for word lines in a MOS DRAM.

As MOS DRAMs have become more highly integrated in recent years, it has become necessary to make patterns finer and to secure capacitor capacitance, and for this reason, it is necessary to make the word line pitch (line and space) submicron.

The present invention can be used as a wiring structure that meets this requirement.

[Conventional technology]

In conventional MOS DRAM, the word line pitch is 1 μm or more, and the backing wiring is also 0.5 μm wide.
Therefore, for the backing wiring, an A1 alloy mainly composed of aluminum (A1) or a laminated structure of an A1 alloy and a high melting point metal was used.

However, with the advancement of integration, the wiring pitch of DRAM (64 Mpi) has become submicron, so the width of the backing wiring is required to be 0.5 μm or less.
It has become difficult to ensure the same level of reliability with conventional wiring mainly made of A1 alloy.

FIG. 4 is a sectional view illustrating a backing wiring using A1 alloy according to a conventional example.

In the figure, l is a word line (gate), 2 is a bit line, 3 is a storage electrode of a capacitor, 4 is a backing wiring, 4
A and 4B are adjacent backing wirings, 5 is a contact hole between the backing wiring and the word line, 6°7.9, 1.0 is an interlayer insulating film, 8 is a counter electrode of a capacitor, 101 is a semiconductor substrate, and 102 is a silicon substrate. It is a field oxide film.

Note that in FIG. 9, the dielectric film of the capacitor between the storage electrode 3 and the counter electrode 8 is omitted.

When the backing wiring 4 is mainly made of A1 alloy, since the melting point is low, the backing wiring 4 is formed on it after the capacitor is formed, so the contact I/pole 5 with the word line 1 becomes deep, and the contact of the backing wiring 4 becomes deep. The step coverage in the hole area is very poor and reduces the reliability of the wiring.

Therefore, a method is being used in which the backing wiring 4 is made of a high melting point metal.

FIG. 5 is a sectional view illustrating a conventional backing wiring using a high melting point metal.

In the figure, a structure is adopted in which the backing wiring 4 is formed using a high melting point metal and is formed below the storage electrode 3 of the capacitor, and the contact hole 5 is made shallow to improve the reliability of the wiring. Since the high melting point metal has a higher resistance value than the A1 alloy, the wiring resistance was not lowered sufficiently.

[Problem to be solved by the invention]

Therefore, if the backing wiring of the word line is formed using a high melting point metal and has a wiring width comparable to that of the word line, the wiring resistance increases and the delay time of the word line increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide word line backing wiring that enables miniaturization and higher reliability of MOS DRAM, reduces wiring resistance, and increases speed.

[Means to solve the problem]

] The solution to the second problem is the word line (]), bit line (2), and capacitor (3) formed on the semiconductor substrate.
.

(8) and a backing wiring (4), the backing wiring (4) is connected in parallel to the word line (1), and the adjacent backing wiring (4A), (4B)
This is achieved by a semiconductor device characterized in that the layers are formed as separate layers and overlap each other with an insulating film interposed therebetween.

[Effect]

In the present invention, since the backing wiring can be formed using a high-melting point metal in a layer lower than the capacitor, the contact hole between the backing wiring and the word line can be made shallower, and as a result, the step coverage can be improved and the reliability of the wiring can be improved. By forming adjoining backing wires at fine intervals using separate layers, the wiring width is expanded in the surplus area of each layer, and the wiring resistance is reduced.

〔Example〕

FIGS. 1A to 1C are a sectional view and a plan view illustrating a backing wiring using a high melting point metal according to an embodiment of the present invention.

In the figure, 1 is a word line (gate).

2 is the pin I line, and 3 is the storage electrode of the capacitor.

4 is the backing wiring, 4A and 4B are the adjacent backing wiring.

5 is a contact hole 6 for backing wiring and word line;
7. 9.1.0 is an interlayer insulating film, and 8 is a counter electrode of the capacitor.

Note that in FIG. 1, the dielectric film of the capacitor between the storage electrode 3 and the counter electrode 8 is omitted.

Here, the adjacent backing wirings 4A and 4B are formed using different layers.

For this reason, roughly speaking, if the width of the punched pattern is matched to the word line with a wiring width equal to the word line pitch, it is possible to secure a wiring width of about three times the word line width for the backing wiring 4A and 4B. Become.

In other words, the wiring resistance is 172 to 1/3 that of the conventional high-melting point metal backing wiring, and this value offsets the disadvantage of high-melting point metals to AI (resistivity is 2 to 3 times higher). It is.

FIG. 1 (1) shows the arrangement of word line 1 linearly for simplicity, and bit line 2 . FIG. 3 is a plan view in which the arrangement of contacts of a storage electrode 3 and a backing wiring 4 of a capacitor is additionally shown.

An enlarged view of part A is shown in FIG. 1(C).

In Fig. 1(C), the backing wirings 4A and 4B had to be routed while avoiding alignment margins with the contact holes of the storage electrodes 3 of the capacitor, and the wiring width became quite wide, like a double layer. , will be restricted by this amount.

In the figure, d indicates the backing wiring 4A or 4B and the capacitor electrode 3.
Indicates the distance between the contact hole and the contact hole.

FIG. 2 is a sectional view illustrating a backing wiring using a high melting point metal according to another embodiment of the present invention.

In this example, adjacent backing wirings 4A and 4B are separated into two layers of capacitors 3 and 8 to prevent mutual coupling.

FIG. 3 is a sectional view illustrating a backing wiring using a high melting point metal according to another embodiment of the present invention.

In this example, adjacent backing wirings 4A and 4B are formed in two layers of capacitors 3 and 8, each in a separate layer.

In this case, the capacitor electrode 3 explained in FIG.
Since there is no restriction on the width of the backing wiring due to the contact hole, the width of the backing wiring can be made wider.

〔Effect of the invention〕

As explained below, according to the present invention, MOS DR
It enables miniaturization and high reliability of AM. A word line backing wiring with reduced wiring resistance was obtained.

As a result, the word line resistance of the MOS DRAM is reduced, and the word line signal delay time can be reduced.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(C) are a sectional view and a plan view illustrating a backing wiring using a high melting point metal according to an embodiment of the present invention. FIG. 2 is a sectional view illustrating a backing wiring using a high melting point metal according to another embodiment of the present invention. FIG. 3 is a sectional view illustrating a backing wiring using a high melting point metal according to another embodiment of the present invention. FIG. 4 is a sectional view illustrating backing wiring using A1 alloy according to a conventional example. FIG. 5 is a sectional view illustrating a conventional backing wiring using a high melting point metal. In fig. 1 is the word line (gate). 2 is the bit line. 3 is the storage electrode of the capacitor. 4 is the backing wiring. 4A and 4B are contact holes 79 for the adjacent backing wirings 5 and the word line. In IO, the interlayer insulating film 8 is the counter electrode of the capacitor. Cross-section of the Ikani pot in Itari suburbs (2) S figure

Claims (1)

[Claims] A MOSDRAM comprising a word line (1), a bit line (2), capacitors (3), (8), and a backing wiring (4) formed on a semiconductor substrate, the backing wiring ( 4) is connected in parallel to the word line (1), and the adjacent backing wirings (4A) and (4B) are formed in separate layers, and are overlapped with each other via an insulating film. Semiconductor equipment.