JPH0897367A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0897367A JPH0897367A JP23182794A JP23182794A JPH0897367A JP H0897367 A JPH0897367 A JP H0897367A JP 23182794 A JP23182794 A JP 23182794A JP 23182794 A JP23182794 A JP 23182794A JP H0897367 A JPH0897367 A JP H0897367A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- semiconductor substrate
- via hole
- semiconductor device
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体基板に形成され
たバイアホールの内側に、コンデンサ等の受動素子を形
成した半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a passive element such as a capacitor formed inside a via hole formed in a semiconductor substrate.
【0002】[0002]
【従来の技術】従来のモノリシック・マイクロ波IC
(MMIC)などの半導体装置は、図3に示すように、
GaAsなどの半導体基板10の表面に、接地電極1
1、電界効果トランジスタ(FET)12などの能動素
子、およびキャパシタ素子13、抵抗素子14、インダ
クタ素子15などの受動素子が形成されて構成されてい
る。そして、その半導体基板10の裏面に、接地金属層
16が形成され、この裏面の接地金属層16と表面の接
地電極11とを、半導体基板10に形成されたバイアホ
ール17を介して接続している。2. Description of the Related Art Conventional monolithic microwave IC
A semiconductor device such as (MMIC) is, as shown in FIG.
The ground electrode 1 is formed on the surface of the semiconductor substrate 10 such as GaAs.
1, active elements such as a field effect transistor (FET) 12 and passive elements such as a capacitor element 13, a resistance element 14, and an inductor element 15 are formed. Then, a ground metal layer 16 is formed on the back surface of the semiconductor substrate 10, and the ground metal layer 16 on the back surface and the ground electrode 11 on the front surface are connected via a via hole 17 formed in the semiconductor substrate 10. There is.
【0003】また、FETなどの接地は、例えば、図4
の回路に示すように、バイパス用のキャパシタC、抵抗
Rなどを介して行われる。このバイパスに使用されるキ
ャパシタCは、通常、ICの他の部分で使用されるキャ
パシタに比べて、数倍から数十倍程度、容量の大きいも
のが必要となる。Further, the grounding of the FET or the like is, for example, as shown in FIG.
As shown in the circuit (1), it is performed via a bypass capacitor C, a resistor R, and the like. The capacitor C used for this bypass usually needs to have a capacitance that is several to several tens of times larger than that of a capacitor used in other parts of the IC.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、バイパ
ス用のキャパシタは、大きな面積を必要として、従来の
手段でこれを半導体基板へ形成した場合、ICチップの
面積が大きくなり、集積度が上がらないという問題があ
った。However, the bypass capacitor requires a large area, and when it is formed on the semiconductor substrate by the conventional means, the area of the IC chip becomes large and the degree of integration cannot be increased. There was a problem.
【0005】したがって、本発明は、基板に形成された
バイアホールの内側に、コンデンサなどの受動素子を形
成することにより、半導体装置の面積を縮小して集積度
を高めた半導体装置を提供することを目的とする。Therefore, the present invention provides a semiconductor device in which a passive device such as a capacitor is formed inside a via hole formed in a substrate to reduce the area of the semiconductor device and increase the degree of integration. With the goal.
【0006】[0006]
【課題を解決するための手段】本発明の課題に対する解
決手段は以下の通りである。 1.バイアホールの形成された半導体基板の表面にIC
の導体金属層などの構成要素が形成され、前記バイアホ
ールの内側に設けられ、かつ、前記表面の導体金属層と
半導体基板裏面の接地金属層との間に接続されて機能回
路を構成するコンデンサ、抵抗、インダクタなどの受動
素子が形成されてなる半導体装置。Means for solving the problems of the present invention are as follows. 1. The IC is formed on the surface of the semiconductor substrate on which the via holes are formed.
And a component which is provided inside the via hole and is connected between the conductor metal layer on the front surface and the ground metal layer on the rear surface of the semiconductor substrate to form a functional circuit. A semiconductor device in which passive elements such as resistors, inductors, etc. are formed.
【0007】2.バイアホールの形成された半導体基板
の表面にICの導体金属層などの構成要素が形成され、
前記バイアホールの内側に、前記半導体基板表面の導体
金属層に導通する金属電極が形成され、この金属電極下
面に絶縁膜が形成され、並びにこの絶縁膜下面および半
導体基板裏面に接地金属層が形成されて、前記表面の導
体金属層と半導体基板裏面の接地金属層との間に、前記
絶縁膜を誘電体とするコンデンサがバイアホールの内側
に形成されてなる半導体装置。2. Components such as a conductor metal layer of the IC are formed on the surface of the semiconductor substrate on which the via holes are formed,
Inside the via hole, a metal electrode is formed which is electrically connected to the conductor metal layer on the surface of the semiconductor substrate, an insulating film is formed on the lower surface of the metal electrode, and a ground metal layer is formed on the lower surface of the insulating film and the rear surface of the semiconductor substrate. Then, a semiconductor device in which a capacitor having the insulating film as a dielectric is formed inside the via hole between the conductor metal layer on the front surface and the ground metal layer on the back surface of the semiconductor substrate.
【0008】3.バイアホールの形成された半導体基板
の表面にICの導体金属層などの構成要素が形成され、
前記バイアホールの内側の一部で、かつ、前記表面の導
体金属層下面から半導体基板裏面にかけて、イオン注入
型抵抗が形成され、前記バイアホールの内側で、かつ、
前記イオン注入型抵抗の主たる部分を除いて、金属電極
が形成され、前記金属電極下面に絶縁膜が形成され、お
よび前記絶縁膜下面および前記イオン注入型抵抗の下部
並びに半導体基板裏面に接地金属層が形成されて、前記
表面の導体金属層と半導体基板裏面の接地金属層との間
に抵抗とコンデンサの並列回路がバイアホールの内側に
形成されてなる半導体装置。3. Components such as a conductor metal layer of the IC are formed on the surface of the semiconductor substrate on which the via holes are formed,
In a part of the inside of the via hole, and from the lower surface of the conductor metal layer on the surface to the back surface of the semiconductor substrate, an ion implantation resistance is formed, and inside the via hole, and
A metal electrode is formed except for the main part of the ion implantation resistance, an insulating film is formed on the lower surface of the metal electrode, and a ground metal layer is formed on the lower surface of the insulation film, the lower portion of the ion implantation resistance, and the back surface of the semiconductor substrate. And a parallel circuit of a resistor and a capacitor is formed inside the via hole between the conductor metal layer on the front surface and the ground metal layer on the back surface of the semiconductor substrate.
【0009】[0009]
【作用】本発明は、半導体基板に形成されたバイアホー
ルの内側に、コンデンサなど広い面積を占有する受動素
子を形成するので、半導体装置の集積度が高まる。According to the present invention, since a passive element occupying a large area such as a capacitor is formed inside the via hole formed in the semiconductor substrate, the degree of integration of the semiconductor device is increased.
【0010】[0010]
【実施例】以下に、本発明の実施例について図面を参照
して説明する。図1は本発明の一実施例に係る半導体装
置の概略断面図を示すものである。同図において、1は
半導体基板で、この半導体基板1の表面には、導体金属
層2a〜2e、絶縁膜3a、3bが設けられている。4
はバイアホールで、例えば、エッチングなどにより半導
体基板1を貫通して形成される。バイアホール4の内側
には、半導体基板1の表面の導体金属層2cに導通する
金属電極5が形成される。6は絶縁膜で、金属層5の下
面(図1において、以下同じ。)に形成される。7は接
地金属層で、絶縁膜6および半導体基板1の裏面に形成
される。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view of a semiconductor device according to an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, and on the surface of the semiconductor substrate 1, conductor metal layers 2a to 2e and insulating films 3a and 3b are provided. Four
Is a via hole and is formed through the semiconductor substrate 1 by etching or the like. Inside the via hole 4, a metal electrode 5 that is electrically connected to the conductor metal layer 2c on the surface of the semiconductor substrate 1 is formed. Reference numeral 6 denotes an insulating film, which is formed on the lower surface of the metal layer 5 (the same applies hereinafter in FIG. 1). A ground metal layer 7 is formed on the back surface of the insulating film 6 and the semiconductor substrate 1.
【0011】本実施例は、以上のような構造よりなる
が、半導体基板1の表面の導体金属層2cと半導体基板
1の裏面の接地金属層7との間に、絶縁膜6を誘電体と
して、コンデンサが形成されていることになる。このコ
ンデンサは、上述のように、バイアホール4の内側に3
次元的立体構造で形成されているので、半導体基板の平
面上に形成されるMIMキャパシタなどと相違して、容
量の大きいものとなる。つぎに、本発明の他の実施例に
ついて図2を参照して説明する。本実施例において、図
1の実施例と同一部分には同一番号を付して、その説明
を省略する。本実施例は、図4に示す回路を具体化した
もので、FETに接続されているコンデンサCと抵抗R
のバイパス回路を、バイアホール4の内側に形成したも
のである。This embodiment has the above-mentioned structure, but the insulating film 6 is used as a dielectric between the conductor metal layer 2c on the front surface of the semiconductor substrate 1 and the ground metal layer 7 on the back surface of the semiconductor substrate 1. , A capacitor is formed. This capacitor is located inside via hole 4 as described above.
Since it is formed in a three-dimensional structure, it has a large capacitance, unlike an MIM capacitor formed on the plane of a semiconductor substrate. Next, another embodiment of the present invention will be described with reference to FIG. In this embodiment, the same parts as those in the embodiment of FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. This embodiment embodies the circuit shown in FIG. 4, and includes a capacitor C and a resistor R connected to the FET.
The bypass circuit is formed inside the via hole 4.
【0012】即ち、バイアホール4の内側の一部に、裏
面からイオンを注入して、半導体基板1の表面の導体金
属層2cに接して半導体基板1の裏面にいたるイオン注
入型抵抗8が形成される。このイオン注入型抵抗8の主
たる部分を除いて、バイアホール4の内側に、金属電極
5が形成される。この金属電極5の下面に、実施例1と
同様に、絶縁膜6が形成される。そして、この絶縁膜6
の下面と半導体基板1の裏面とに、接地金属層7が形成
される。That is, ions are implanted from a back surface into a part of the inside of the via hole 4, and an ion implantation resistor 8 reaching the back surface of the semiconductor substrate 1 is formed in contact with the conductor metal layer 2c on the surface of the semiconductor substrate 1. To be done. A metal electrode 5 is formed inside the via hole 4 except for the main part of the ion implantation resistor 8. An insulating film 6 is formed on the lower surface of the metal electrode 5 as in the first embodiment. And this insulating film 6
A ground metal layer 7 is formed on the bottom surface of the semiconductor substrate 1 and the back surface of the semiconductor substrate 1.
【0013】本実施例は、以上のような構造よりなる
が、イオン注入型抵抗8と絶縁膜6によるコンデンサと
が、半導体基板1の表面の導体金属層2cと半導体基板
1の裏面の接地金属層7との間に、並列になってバイア
ホール4の内側に形成されている。したがって、本実施
例は、実施例1に比べて更に集積度の高いものとなる。The present embodiment has the above-described structure, but the ion-implanted resistor 8 and the capacitor made of the insulating film 6 are used as a conductor metal layer 2c on the front surface of the semiconductor substrate 1 and a ground metal on the back surface of the semiconductor substrate 1. It is formed in parallel with the layer 7 inside the via hole 4. Therefore, the present embodiment has a higher degree of integration than the first embodiment.
【0014】[0014]
【発明の効果】本発明は、半導体基板に形成されたバイ
アホールの内側に、このバイアホールの3次元的立体構
造を利用して、コンデンサなど広い面積を占有する受動
素子を立体的に形成するので、例えば、容量の大きいコ
ンデンサなどを作製できる。また、広い面積を占有する
受動部品をバイアホールの内側に形成するので、その
分、半導体装置の面積を小さくすることができ、集積度
を高めることができる。According to the present invention, a passive element occupying a large area such as a capacitor is three-dimensionally formed inside a via hole formed in a semiconductor substrate by utilizing the three-dimensional structure of the via hole. Therefore, for example, a capacitor having a large capacity can be manufactured. In addition, since the passive component occupying a large area is formed inside the via hole, the area of the semiconductor device can be reduced correspondingly, and the degree of integration can be increased.
【図1】 本発明の一実施例に係る半導体装置の断面概
略図FIG. 1 is a schematic sectional view of a semiconductor device according to an embodiment of the present invention.
【図2】 本発明の他の実施例に係る半導体装置の断面
概略図FIG. 2 is a schematic sectional view of a semiconductor device according to another embodiment of the present invention.
【図3】 従来例の半導体装置の断面概略図FIG. 3 is a schematic sectional view of a conventional semiconductor device.
【図4】 本発明と従来例とに共通のバイパス回路を備
えたFET回路図FIG. 4 is a FET circuit diagram including a bypass circuit common to the present invention and a conventional example.
1 半導体基板 2a〜2e 導体金属層 3a、3b 絶縁膜 4 バイアホール 5 金属電極 6 絶縁膜 7 接地金属層 8 イオン注入型抵抗 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2a-2e Conductor metal layer 3a, 3b Insulating film 4 Via hole 5 Metal electrode 6 Insulating film 7 Grounding metal layer 8 Ion implantation resistance
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 27/095 H01L 27/04 P 9171−4M 29/80 V 9171−4M E ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI Technical display location H01L 27/095 H01L 27/04 P 9171-4M 29/80 V 9171-4M E
Claims (3)
表面にICの導体金属層などの構成要素が形成され、前
記バイアホールの内側に設けられ、かつ、前記表面の導
体金属層と半導体基板裏面の接地金属層との間に接続さ
れて機能回路を構成するコンデンサ、抵抗、インダクタ
などの受動素子が形成されてなる半導体装置。1. A component such as a conductor metal layer of an IC is formed on the surface of a semiconductor substrate on which a via hole is formed, is provided inside the via hole, and the conductor metal layer on the surface and the back surface of the semiconductor substrate. A semiconductor device in which passive elements such as capacitors, resistors, and inductors, which are connected to the ground metal layer of, and which form a functional circuit, are formed.
表面にICの導体金属層などの構成要素が形成され、前
記バイアホールの内側に、前記半導体基板表面の導体金
属層に導通する金属電極が形成され、この金属電極下面
に絶縁膜が形成され、並びにこの絶縁膜下面および半導
体基板裏面に接地金属層が形成されて、前記表面の導体
金属層と半導体基板裏面の接地金属層との間に、前記絶
縁膜を誘電体とするコンデンサがバイアホールの内側に
形成されてなる半導体装置。2. A constituent element such as a conductor metal layer of an IC is formed on the surface of a semiconductor substrate on which a via hole is formed, and a metal electrode electrically connected to the conductor metal layer on the surface of the semiconductor substrate is provided inside the via hole. An insulating film is formed on the lower surface of the metal electrode, and a ground metal layer is formed on the lower surface of the insulating film and the back surface of the semiconductor substrate, and between the conductor metal layer on the front surface and the ground metal layer on the back surface of the semiconductor substrate. A semiconductor device in which a capacitor having the insulating film as a dielectric is formed inside a via hole.
表面にICの導体金属層などの構成要素が形成され、前
記バイアホールの内側の一部で、かつ、前記表面の導体
金属層下面から半導体基板裏面にかけて、イオン注入型
抵抗が形成され、前記バイアホールの内側で、かつ、前
記イオン注入型抵抗の主たる部分を除いて、金属電極が
形成され、前記金属電極下面に絶縁膜が形成され、およ
び前記絶縁膜下面および前記イオン注入型抵抗の下部並
びに半導体基板裏面に接地金属層が形成されて、前記表
面の導体金属層と半導体基板裏面の接地金属層との間に
抵抗とコンデンサの並列回路がバイアホールの内側に形
成されてなる半導体装置。3. A semiconductor element such as a conductor metal layer of an IC is formed on the surface of a semiconductor substrate on which a via hole is formed, and the semiconductor is formed on a part of the inside of the via hole and from the lower surface of the conductor metal layer on the surface. An ion-implanted resistance is formed over the back surface of the substrate, a metal electrode is formed inside the via hole, and except for a main portion of the ion-implanted resistance, and an insulating film is formed on the lower surface of the metal electrode. A ground metal layer is formed on the lower surface of the insulating film, the lower portion of the ion implantation resistor, and the back surface of the semiconductor substrate, and a parallel circuit of a resistor and a capacitor is provided between the conductor metal layer on the front surface and the ground metal layer on the back surface of the semiconductor substrate. A semiconductor device having a via formed inside a via hole.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23182794A JPH0897367A (en) | 1994-09-27 | 1994-09-27 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23182794A JPH0897367A (en) | 1994-09-27 | 1994-09-27 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0897367A true JPH0897367A (en) | 1996-04-12 |
Family
ID=16929646
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23182794A Pending JPH0897367A (en) | 1994-09-27 | 1994-09-27 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0897367A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100328710B1 (en) * | 1999-08-23 | 2002-03-20 | 박종섭 | Inductor and fabricating method thereof |
JP2009515356A (en) * | 2005-11-08 | 2009-04-09 | エヌエックスピー ビー ヴィ | Trench capacitor device suitable for separating applications in high frequency operation |
US20120133020A1 (en) * | 2010-11-30 | 2012-05-31 | Stmicroelectronics S.A. | Semiconductor device comprising a capacitor and an electrical connection via and fabrication method |
US8841749B2 (en) | 2010-11-30 | 2014-09-23 | Stmicroelectronics Sa | Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method |
US9589917B1 (en) * | 2016-03-21 | 2017-03-07 | Raytheon Company | Microwave monolithic integrated circuit (MMIC) having integrated high power thermal dissipating load |
WO2020179452A1 (en) * | 2019-03-01 | 2020-09-10 | ソニーセミコンダクタソリューションズ株式会社 | Capacitative element, semiconductor element substrate, and electronic device |
US11610933B2 (en) | 2018-02-13 | 2023-03-21 | Stmicroelectronics (Crolles 2) Sas | Back-side illuminated image sensor |
-
1994
- 1994-09-27 JP JP23182794A patent/JPH0897367A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100328710B1 (en) * | 1999-08-23 | 2002-03-20 | 박종섭 | Inductor and fabricating method thereof |
JP2009515356A (en) * | 2005-11-08 | 2009-04-09 | エヌエックスピー ビー ヴィ | Trench capacitor device suitable for separating applications in high frequency operation |
US20120133020A1 (en) * | 2010-11-30 | 2012-05-31 | Stmicroelectronics S.A. | Semiconductor device comprising a capacitor and an electrical connection via and fabrication method |
US8841748B2 (en) * | 2010-11-30 | 2014-09-23 | Stmicroelectronics Sa | Semiconductor device comprising a capacitor and an electrical connection via and fabrication method |
US8841749B2 (en) | 2010-11-30 | 2014-09-23 | Stmicroelectronics Sa | Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method |
US9589917B1 (en) * | 2016-03-21 | 2017-03-07 | Raytheon Company | Microwave monolithic integrated circuit (MMIC) having integrated high power thermal dissipating load |
US11610933B2 (en) | 2018-02-13 | 2023-03-21 | Stmicroelectronics (Crolles 2) Sas | Back-side illuminated image sensor |
WO2020179452A1 (en) * | 2019-03-01 | 2020-09-10 | ソニーセミコンダクタソリューションズ株式会社 | Capacitative element, semiconductor element substrate, and electronic device |
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