JPS6334560B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of configuring a high-speed, low power consumption MOS type semiconductor memory, and particularly to a method of configuring a complementary MOS type semiconductor memory.

[Background of the invention]

2. Description of the Related Art Conventionally, in MOS type semiconductor memories, n-MOS memory consisting of only transistors of a single conductivity type and complementary type memory consisting of a combination of transistors of different conductivity types such as p and n channels are known. However, the former has the disadvantage of high power consumption. For this reason, when a large-scale memory is used, for example, 65K bits or more, the temperature of the chip rises mainly due to the power consumption of peripheral circuits, which limits the degree of integration. Furthermore, although the latter has low power consumption, the cell area per bit is large, and a large degree of integration cannot be achieved.

On the other hand, in a dynamic MOS semiconductor memory that includes a dynamic memory cell circuit consisting of a MOS transistor and a capacitor and a word line drive circuit, the MOS transistor of the memory cell circuit and the MOS transistor of the word line drive circuit are of the same conductivity type. In some cases, the threshold voltage Vth of the MOS transistor causes a level loss of rewritten information when rewriting information to the memory cell after reading information from the memory cell, so such level loss does not occur. It is necessary to take such circuit measures (for example, a word line boost circuit).

[Purpose of the invention]

An object of the present invention is to provide a MOS semiconductor memory that can suitably rewrite information to memory cells.

[Summary of the invention and examples]

Outline of typical inventions disclosed in this application is as follows.

That is, a memory cell circuit consisting of a p-channel MOS transistor 40 and a capacitor 44, a data line 64 connected to the source or drain of the p-channel MOS transistor 40, and a gate connected to the p-channel MOS transistor 40. word line 67 and the word line 67
n-channel with source or drain connected to
The sense amplifier circuit includes a MOS transistor 38 and a sense amplifier circuit connected to the data line 64, and the sense amplifier circuit has first inverter circuits 58 and 59 whose inputs are connected to the data line 64, and whose inputs are connected to the It consists of second inverter circuits 57 and 56 connected to the output of the first inverter circuit and whose output is connected to the data line, and the source and drain paths of the first and second inverter circuits are connected in series. The word line 67 includes p-channel MOS transistors 58, 57 and n-channel MOS transistors 59, 56.
The word line is selected by bringing the word line 67 to a low level through the n-channel MOS transistor 38 whose source or drain is connected to the word line 67.

Therefore, n-channel MOS transistor 3
8 is turned on and the word line 67 becomes low level, the p-channel type MOS transistor 40 of the memory cell circuit is turned on and the digital information accumulated in the capacitor 44 is transmitted to the data line 64. In this way, the digital information transmitted to the data line 64 is converted into digital information "1" of the power supply voltage V _DD or digital information of the ground voltage by the sense amplifier circuits 58, 59, 57, and 56 each having a complementary MOS transistor configuration. The information is completely amplified to the level of “0”.

If digital information "1" is stored in the capacitor 44 of the memory cell circuit, the stored voltage level will drop due to natural discharge, etc., but the data line 64 will be completely amplified by the sense amplifier circuit with complementary MOS transistor configuration. information is p-channel type
The data is rewritten into the capacitor 44 via the MOS transistor 40. At this time, p-channel type MOS
The portion of the transistor 40 connected to the data line 64 operates as a source, the portion connected to the capacitor 44 operates as a drain, and the gate is controlled to a low level by the n-channel MOS transistor 38. Capacitor 44 has power supply voltage
The digital information "1" of V _DD is rewritten without loss of threshold voltage between the gate and source of the MOS transistor, making so-called full write operation possible.

Examples of the present invention will be described in detail below.

1 and 2 are cross-sectional views of a complementary MOS semiconductor memory according to an embodiment of the present invention.

An n-channel MOS transistor and a p-channel MOS transistor are provided as a peripheral circuit L on an n-type substrate 1, and a memory cell M is formed in the n-type substrate. In FIG. 1, a P well 2 (the impurity concentration is about 10 ¹⁵ to 10 ¹⁷ /cm ³ ) is formed in a substrate 1, and n ⁺ diffusion layers for a source 3 and a drain 4 are provided in this P well. It is made into an n-channel transistor. Furthermore, a source 5 and a drain 6 are formed in the substrate 1 to form a p-channel MOS transistor. Note that 9 and 12 are gates, 8, 10, and 1, respectively.
1 and 13 are source and drain electrodes.
On the other hand, the memory cell includes an inversion layer capacitor formed directly under the silicon layer 14 and a silicon transfer electrode 15.
and a p ⁺ diffusion layer 7 which becomes a data line. Note that 16 is an insulating layer.

One feature of this embodiment is that memory cells are formed with data lines on a substrate with relatively low impurity concentration.

Figure 2 shows a short channel with a channel length of 2 μm or less.
This is an example in which the peripheral circuit is configured using MOS transistors. P well 1 formed on n substrate 17
8, an n-channel MOS transistor is provided with the n ⁺ diffusion layers 20 and 21 as sources and drains.
Next, an n-type well 19 having a higher concentration than the substrate is formed partially in the substrate, and a p ⁺ layer 22,
23 is provided as the source and drain and p channel
It is used as a MOS transistor and as a peripheral circuit L. In addition, 25 and 26 are gates, 2
9, 30, 31, 32 indicate electrodes. The part of the memory cell M is the same as that in FIG. 1, and 27 is a silicon layer;
28 is a silicon transfer electrode, 24 is a p ⁺ diffusion layer which becomes a data line, and 100 is an insulating layer.

FIGS. 1 and 2 show examples in which complementary peripheral circuits and memory cells are formed on an n-type substrate and a low impurity concentration substrate. The advantages of this configuration are as follows.

(1) By using complementary peripheral circuits and memory cells configured on an n-type substrate, an extremely low power memory can be constructed. According to experiments, it was possible to achieve a power reduction of 1/7 to 1/10 compared to conventional n-MOS.

(2) Since the peripheral circuits can be complementary, power consumption is low and it is suitable for increasing capacity.

(3) By adopting a structure with a well as shown in FIG. 2, the channel length of both p-channel and n-channel transistors can be reduced to 2 μm or less, and the speed of peripheral circuits can be increased.

Furthermore, adopting the configuration of this embodiment has the following advantages.

(4) The transistor formed under the transfer electrode (15 in FIG. 1 or 28 in FIG. 2) of the memory cell is used with its source and drain alternated.
In such usage, charges are injected into the oxide film, especially when the channel is short (approximately 2 μm or less), resulting in more stable operation.

In other words, as shown below, a p-channel MOS transistor has better stability due to charge injection than an n-channel MOS transistor, so by adopting the configuration of the present invention, stable operation can be ensured. .

Figure 3 shows a symmetrical MOS in which the source and drain regions have the same shape (oxide film T _OX = 1000 Å, n
Impurity concentration in case of channel ~10 ¹⁵ /cm ⁸ , p
In the case of a channel, it is ~5×10 ¹⁵ /cm ⁸ . ) shows experimental results using transistors. The figure shows that a certain voltage V is applied to the drain, the drain is operated for 30 seconds, the drain and source are replaced, the threshold voltage is measured, and the limit voltage value at which the threshold voltage shifts to a value different from the original value is determined. It is shown as a function of channel length (L _eff ). From the figure, the P channel can operate more stably than the N channel. Also, it is possible to shorten the channel.

(5) On n-type substrates, there are fewer defects and less leakage current. Therefore, a long refresh time can be obtained.

The complementary MOS semiconductor memory of this embodiment becomes more effective by applying a voltage V _DD + higher than the high level voltage V _H of the data line to its substrate. It is sufficient to use a general circuit as a means for applying this V _DD +. It is desirable to make this voltage V _DD + high so as to reduce the data line capacitance as much as possible, but on the other hand, the absolute value of the threshold voltage (V _Th ) of the p-channel MOS becomes higher than necessary due to this bias. It is necessary to prevent this from happening. For example, the accumulated charge in memory is (V _DD − |
V _TH |) C _OX , but if V _DD is 5V, |V _TH |
When the voltage exceeds 2V, this value drops rapidly and becomes undetectable by the sense amplifier. Therefore,
When applying substrate bias, the V _TH of p-MOS is
2V or less is preferable. Similarly, from the viewpoint of operating speed of peripheral circuits, 2V or less is preferable. Desired _VDD
For example, when the oxide film thickness T _OX directly under the gate is 500 Å, the substrate impurity concentration N = 10 ¹⁵ cm ^-3 , and V _DD = 5 V, if V _DD + is set to 8 to 10 V, the data line capacitance is It will be about 2/3 to 1/2.

By taking such measures, the following advantages are further produced.

(6) Since the bottom of the data line 24 of the memory cell is in contact with a low concentration layer, the capacitance is small, and since it is always reverse biased, the capacitance between the data line and the substrate can be further reduced. . Therefore, when the ratio C _S /C _D of the storage capacitance C _S between the inversion layer in the memory cell and the storage electrode 27 to the data line capacitance C _D is reduced to the allowable range of the sense amplifier, C _S is small. Therefore, the area of the cell can be reduced.

FIG. 4 is a circuit diagram according to a specific embodiment of the present invention. In the same figure, a P-channel MOS transistor 33 and an N-channel MOS transistor 34
~37 form an address decoder, and are connected to a p-channel MOS transistor 51 and an n-channel MOS transistor.
MOS transistors 52 and 38 form a word line drive circuit and select word line 67. In reality, when the timing pulse _φ The selection is made by This allows p
The cell consisting of channel MOS transistor 39 and capacitor 43 and the cell consisting of p-channel MOS transistor 40 and capacitor 44 are in the read state. For example, the charge on C _S is transferred to the capacitor C _D 47 attached to the data line 64, which in turn connects the P-channel and N-channel MOS transistors that form the sense amplifier.
Sensed by transistors 55-60. 5
Reference numerals 3 and 61 indicate switch transistors of the sense amplifier. That is, when the n-channel MOS transistors 38 and 52 are turned on and the word line 67 becomes low level, the p-channel MOS transistor 40 of the memory cell circuit is turned on and the digital information stored in the capacitor 44 is transferred to the data line 6.
4. In this way, the data line 64
The digital information transmitted to the sense amplifier circuits 58, 59, 5 each having a complementary MOS transistor configuration
7 and 56, it is completely amplified to the level of digital information "1" of the power supply voltage V _DD or digital information "0" of the ground voltage.

If digital information "1" is stored in the capacitor 44 of the memory cell circuit, the stored voltage level will drop due to natural discharge, etc., but the data line 64 will be completely amplified by the sense amplifier circuit with complementary MOS transistor configuration. information is p-channel type
The data is rewritten into the capacitor 44 via the MOS transistor 40. At this time, p-channel type MOS
The portion of the transistor 40 connected to the data line 64 operates as a source, the portion connected to the capacitor 44 operates as a drain, and the gate is controlled to a low level by the n-channel MOS transistor 38. Capacitor 44 has power supply voltage
The digital information "1" of V _DD is rewritten without loss of threshold voltage between the gate and source of the MOS transistor, making so-called full write operation possible. In the figure, in order to reduce the data line capacitance of the memory cell, the sense amplifier is driven at a slightly lower voltage V _DD with respect to the substrate terminal V _DD + so that the data line is always in a reverse bias state. Even if other peripheral circuits are operated at V _DD , V _DD +
You can also run it with For example, as V _DD +
Experiments were conducted with values of 10V and V _DD of 7V, and it was confirmed that these circuits operated well.

FIGS. 5 and 6 show other embodiments. FIG. 5 will be explained. Concentration 10 ¹² on the surface of 10Ωcm n-substrate 69
The n-layer 71 of arsenic of cm ^-2 is diffused to a thickness of about 1 μm (generally, the impurity concentration of the n-layer 71 is about 10 ¹² to 10 ¹³ /cm ² ), and this portion is 1 Ω·cm. 71,
73 is an n-channel formed in the P-well 70
The source and drain of the MOS, 74 and 75 are the p+ layer 7 that becomes the source and drain of the P channel MOS.
6 is a p+ layer which becomes a data line. At this time, the impurity concentration of the p-well layer is about 10 ¹⁵ to 10 ¹⁷ /cm ⁸ . The source and drain may be manufactured with normal dimensions. The feature of this structure is that the data line and the source/drain layers of the p-channel MOS in the peripheral circuit are surrounded by layers with relatively high concentration, so that the threshold voltage of the p-channel MOS and the field part MOS is It will be higher than in Figure 2. However, since these bottom portions are in contact with a low-concentration substrate, the data line capacitance can be reduced.

Note that even if the n-layer 71 is diffused deeper than the bottom of the data line, if the difference is within 0.5 μm,
Experiments have shown that since the capacitance is almost depleted, the capacitance can be similarly reduced.

FIG. 6 is almost the same as FIG. 2, but a SiO ₂ film 103 is formed on the n-layer substrate 85 by local oxidation, gate oxidation is performed, and then a silicon electrode is deposited. Thereafter, a boron-diffused P-well layer 86 and arsenic-diffused n-channel MOS source/drain layers 87 and 88 are successively formed by the double diffusion method by diffusion from the same window. After that, the source/drain p+ of the P channel MOS
Layers 89, 90 and data line p+ layer 91 are diffused.

7 has almost the same structure as the embodiment shown in FIG. 5, except that in the embodiment shown in FIG. 10 ¹⁶ cm ^-3 ) is formed only in the region where the P channel transistor is formed, and this n layer 107
07 and the p-well 106 are formed so as to be separated from each other and not in contact with each other. By adopting such a structure, the impurity concentration of the substrate that determines the threshold voltage of each of the n-channel and p-channel transistors can be determined independently of each other, which has the advantage of increasing the degree of freedom.

In addition, each number in FIG. 5, FIG. 6, and FIG. 7 is as follows.

79, 81, 82, 87, 94, 96, 97,
99, 115, 117, 118, 120 are electrodes,
80, 83, 95, 98, 116, 119 are gates, 78, 93, 114 are silicon layers, 77, 9
2, 113 are transfer electrodes, 76, 91, 112 are diffusion layers that become data lines, and 101, 102 are insulating layers.

FIG. 8 shows an example of an element manufacturing process applying a local oxidation method generally called the LOCOS method. First, using a thick field oxide film 302 formed by selective oxidation on a substrate 301 as a mask,
A p-type well 304 and an n-well 306 are formed (FIGS. 8A, B, and C). thin gate oxide film 30
1, the first layer of polycrystalline silicon 30 is formed.
7,308 is deposited, and p-type impurities are added at a high concentration only to the p-channel transistor in the peripheral circuit and the polycrystalline silicon 308 on the memory cell portion (FIG. 8D). An oxide film 311 is formed only in the memory cell area, and then a pattern is formed on the polycrystalline silicon by photoetching to form the gate electrode 31.
2, 313 and a storage electrode 352 are formed (FIG. 7E). After that, after forming a thin oxide film 314, a second layer of polycrystalline silicon 315 is deposited (FIG. 8F), and the source and
N-type impurities are added to the drain region 322 and the second layer of polycrystalline silicon 315 at a high concentration (FIG. 8G). Next, an oxide film 316 is formed on the N-channel transistor section and the memory cell transfer electrode 360, and the p
The p-type impurity in the p-well 304 is added at a high concentration.
A high concentration layer 317, a source and a drain 318 of a p-channel transistor, and a data line 319 of a memory cell are formed (FIG. 8H). Next, a surface protective film 320 is applied, and finally an electrode 321 is formed (FIG. 8I).

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a complementary MOS semiconductor memory according to an embodiment of the present invention, FIG. 2, FIG. 5, FIG.
FIG. 7 is a sectional view of a memory showing an embodiment of the present invention;
Fig. 3 is a diagram showing the maximum operating voltage of p-channel and n-channel MOS, Fig. 4 is a circuit diagram to which the present invention is specifically applied, and Fig. 8 is a diagram showing an example of the manufacturing process of the memory of the present invention. be. 1, 17, 69, 85, 104, 301 are semiconductor substrates, 2, 18, 19, 70, 86, 106,
304, 306 are well impurity regions, 3, 4, 2
0,21,71,73,87,88,107,1
08, 109, 322 are n-type impurity regions, 5,
6, 7, 22, 23, 24, 74, 75, 76,
89,90,91,110,111,112,3
18, 319 are p-type impurity regions, 9, 12, 2
5, 26, 80, 83, 95, 98, 116, 1
19, 312, 313 are gate electrodes, 14, 2
7, 78, 93, 114, 352 are capacitive electrodes, 1
5, 28, 77, 92, 113, 360 are transfer electrodes, 16, 100, 101, 102, 103, 1
05, 302, 303 are insulating films, 8, 10, 1
1, 13, 29, 30, 31, 32, 79, 8
1, 82, 84, 94, 96, 97, 99, 11
5, 117, 118, 120, 321 are electrodes, 3
20 is a protective film.

Claims (1)

[Claims] 1. A memory cell circuit including a p-channel MOS transistor and a capacitor;
a data line connected to the source or drain of the MOS transistor, a word line connected to the gate of the p-channel MOS transistor, an n-channel MOS transistor whose source or drain is connected to the word line, and the data a first inverter circuit whose input is connected to the data line; and a sense amplifier circuit whose input is connected to the output of the first inverter circuit and whose output is connected to the data line. and a second inverter circuit connected to the data line, and the first and second inverter circuits each include a p-channel MOS transistor and an n-channel MOS transistor whose source/drain paths are connected in series.
by bringing the word line to a low level through the n-channel MOS transistor, the source or drain of which is connected to the word line;
Complementary type characterized by word line selection
MOS semiconductor memory. 2. An output signal of a word line selection circuit composed of complementary MOS transistors is input to the gate of the n-channel MOS transistor whose source or drain is connected to the word line. Complementary type described in range 1
MOS semiconductor memory. 3. An output signal from a complementary MOS inverter circuit is input to the source or drain of the n-channel MOS transistor whose source or drain is connected to the word line, or , the complementary type described in Section 2
MOS semiconductor memory.