JPS6211261A - Cmos memory device - Google Patents

Abstract

PURPOSE:To obtain higher operation speed of a CMOS memory by making the concentration of the second conductive type well in which a memory cell matrix is formed lower than the concentration of the second conductive type well in which a peripheral circuit is formed. CONSTITUTION:On an N-type substrate 10, a memory cell matrix is formed in a P-type well 10 and a peripheral circuit in the memory cell part is smaller than a leakage current produced in the peripheral circuit, a high-speed operation is realized by reducing diffusion capacitance by making the impurity concentrations N1 and N2 of the wells 10 and 11 respectively conform the relation N1<N2. It is to be noted that, although the larger than channel width of a MOSFET, the larger an impact ionization current; the channel width of an FET with memory cells to the extent of 64kbit is less than 1/5 of the channel widths of the elements most frequently used in the peripheral circuit and its impact ionization current is also less than 1/5 of the current in the peripheral circuit so that the relation N1<N2 can be realized and the resistance to latching-up can be increased. With this concentration composition, a CMOS memory with a high operation speed can be obtained without deteriorating the resistance to latching-up.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a CMOS memory device.〇 [Prior Art] General KC? The layout of a viOS memory device can be roughly divided into a memory cell matrix portion and a peripheral circuit portion. The memory cell matrix part is a word line,
The peripheral circuitry consists of a digit line and a memory cell, while the peripheral circuitry selects a memory cell corresponding to an externally applied address signal and writes or outputs data to that memory cell. consists of parts.

By the way, CMOS memory device ri using MOSFET
A mold shell is formed with a second conductor having a complementary relationship with the first conductivity type substrate, and the second conductivity %: the second conductivity 1
! A first conductivity type MOSFET is formed in the second conductivity type well. Below, a P-type well is provided on the N-type substrate, and the N-type well is used as a transfer gate to transfer data between the memory cell and the digit line.
A case will be described in which a channel type MO8F B '1'' is used, but the same applies to the case where a P channel MO8FET is used as the transfer gate.

Conventionally, in CMOS memory devices, the impurity density of the P-type well is rarely the same across all Pfi wells in the chip. FIG. 2 is a plan view of a CMOS memory device, and the well region is shaded to make it easier to see.

In FIG. 2, 20 is a P-type well in which a memory cell matrix is formed, 21 is a P-type well in which a peripheral circuit is formed, and 22 is an N-type substrate in which a peripheral circuit is formed. Conventionally, the 20th P-type well and the 21st P-type well had the same impurity concentration.

[Problem that the invention seeks to solve]

The above-mentioned conventional cMOS memory devices have a drawback of slow operation speed because the impurity concentration of the P-type well is constant within the chip. The reason is explained below.

First, it will be described how the impurity concentration of P-type 9L is related to the characteristics of a semiconductor memory device.

First of all, the operating speed is fast, with a short simulation time of 11 to charge and discharge the capacitance in the circuit.

Therefore, it goes without saying that the capacitance to be charged and discharged is /J%
Very fast. The silence and capacity can be roughly divided into CM08FET.
It can be divided into three types: the gate capacitance of MO8FET (CM08F), the source and drain diffusion layer capacitance of T, and the other interconnect capacitance. Of these, the source/drain diffusion layer capacitance of N-channel MO8FET depends on the impurity concentration of the P-type well. do.

It is known that if the capacitance of the N-type diffusion layer formed in the P-type well circle is Cd, and the impurity concentration of the P-type well is N, the relationship aocJK holds true. That is,
The higher the impurity concentration, the greater the diffusion layer capacitance and therefore the slower the operating speed.

In particular, the digit line has a large capacitance because it is connected to a large number of memory cells, of which the diffusion layer capacitance of the source (or drain) of the transfer gate MO8FET of the memory cell accounts for about 60 to 70%. MOSFETs used in memory cells have a minimum channel width because it is necessary to reduce the memory cell size, so the speed at which memory cell data is transmitted digitally during reading is significantly delayed, especially when the diffusion layer capacitance is large. It's hot.

Therefore, in order to increase the operating speed, it is better to lower the iP type Tawell impurity concentration, but this will deteriorate the latch-up breakdown voltage. The latch-up phenomenon will be explained below with reference to FIGS. 3 and 4.

FIG. 3 is a cross-sectional view of the HCMOS memory device.

In FIG. 3, 30 is a negative-type substrate, 31 is a P-type well 3
28, 32D are source and drain diffusion layers of P-channel MO8FET, 338, 33D are N-channel MO8F
ET source and drain diffusion layers; 34 is a gate diffusion film;
35 is a game made of polysilicon)! 36 is a substrate contact for bringing the N-type substrate 30 to a power supply potential; 37 is a well contact for bringing the P-type well to ground potential;
38 is an input terminal, 39 is an output terminal, and 50 is a power source.

FIG. 4 is a circuit diagram of the CMOS memory device shown in FIG. 3.

In FIG. 4, 40 is the substrate resistance of the N-type substrate 30, and 41
is the well resistance of the P-type well 31, and 44 is the P-type well 31.
42 is an NPN bihole transistor whose collector is the N-type substrate 30, the P-star transistor 31 is the base, and the emitter is the source diffusion layer 338 of the N-channel MO8FET; 43 is the P-channel transistor; A P transistor with the source diffusion layer 328 as the emitter, the N-type substrate 30 as the base, and the P-type well 31 as the collector.
It is an NP bipolar transistor.

Now, if there is no leakage current flowing into the P-type relay 31, all the P-N junctions in the path are reverse biased, so the PNP) transistor 43 and the NPN) transistor 42 are turned off, and the transistor 42 is turned off. Latch-up does not occur.

However, due to impact ionization that occurs when the N-channel MO8FET operates, the P-type well 31Kt source 5
When a leakage current flows from the well resistor 41 through the resistor 44, the potential near the source of the leakage current rises above the ground potential due to the well resistor 41. The potential increase is determined by the leakage current value and the well resistance between the part where the leakage current occurs and the well contact 37, so the leakage current increases, that is, the equivalent resistance 44
The smaller the value, the greater the potential rise. As the potential rise becomes steeper, P-type well 31 and N-channel MO8F
The PN junction between the ET and the source diffusion layer 338 connected to the ground potential is in a forward bias state, and a current flows in the direction.

That is, NPN transistor 420 in FIG.
A pace current flows and the NPN transistor 42 is turned on. Therefore, a collector current flows from the N-type substrate 30 corresponding to the collector toward the source diffusion layer 338 of the N-channel MO8FET. Since the collector current flows from the substrate contact 36 to the Pa well 31 through the substrate resistor 40, a potential drop occurs within the N-type substrate 30. Then, the source diffusion layer 328 connected to the P-type MO8FETO power supply potential is used as the emitter, and the substrate is used as the base.
P) The PN junction between the pace emitter of the transistor 43 is forward biased, and the PNP transistor 4
3 is turned on. When the PNP) transistor 43 is turned on, the Pfi well potential further increases, which also causes the h-type substrate potential to decrease.

In this way, turn the N-type board 30 from the power supply to the ground.
A large current flows from the P-type well 31 through the P-type well 31. This is the latch-up phenomenon.

In this way, latch-up occurs due to the presence of leakage current, the resulting rise in the potential of the P-type well 31, and the drop in the potential of the N-type substrate 20. The potential increase of the P-type well 31 and the decrease of the potential of the N-type substrate 30 increase as the leakage current increases.
#1 has a large substrate and well resistance of 40°41. On the other hand, the substrate ρ-well resistance 40° 41 is approximately inversely proportional to the impurity concentration of the N-type substrate 30 and the P-type well 31. That is,
The impurity concentration of the N-type substrate 30 or P-type well 31 is low #
First, the substrate and well resistances 40 and 41 are high, so double-up is more likely to occur.

As explained above, from the viewpoint of high-speed operation, it is preferable that the impurity concentration is low, and from the viewpoint of latch-up, it is preferable that the impurity concentration is high.

In recent years, the density of semiconductor memory devices has significantly increased, and as a result, the channel length of the MOSFETs used has increased.
The gate oxide film thickness is becoming shorter and shorter, and the gate oxide film thickness is becoming thinner. As a result, the impact ionization current generated when the MO8FET operates has increased significantly, and the impurity concentration in the substrate and well has become high to prevent latch-up.

Therefore, there is a drawback that it is difficult to realize high-speed operation.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a CMOS memory device which eliminates the above drawbacks, is capable of high-speed operation, and is less prone to latch-up phenomena.

[Means for solving problems]

The CMOS memory device of the present invention is one in which a second conductivity type well is formed in a -th conductivity*m semiconductor substrate, and a mesoricell matrix and a peripheral circuit are formed in the second conductivity type well. The impurity concentration of the second conductive type well in which the memory cell matrix is formed is lower than that of the second conductive type well in which the peripheral circuit portion is formed.

〔Example〕

Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a plan view of one embodiment of the present invention.

In FIG. 1, 10 is a P-type well in which a memory cell matrix is formed, 11 is a P-type well in which a peripheral circuit other than the memory cell matrix is formed, and 12 is an N-type substrate in which a peripheral circuit is formed. Assume that the impurity concentration of the P-type well 10 in which the memory cell matrix is formed is N1.

If the impurity concentration of the P-type well 11 in which the peripheral (b) path is formed is N, then there is a relationship of NI<Nz.

In this way, the memory cell matrix is formed.
The reason why the impurity concentration in the mold well 10 can be lowered is because the leakage current generated in the memory cell is smaller than the leakage current generated in the peripheral circuitry.The cause of latch-up is the leakage current due to impact ionization in the MOSFET. Mainly, 9. Since the impact ionization current in a MOSFET is proportional to the magnitude of the channel current of MO8P''ET, the larger the channel width of the MOSFET, the larger the impact ionization current.

Normally, in a memory device of about 64 kilobits, the channel width of the L-mesh cell MOSFET is 115 or less than the channel width of the MOSFET most often used in peripheral circuits, so the impact ionization current in the memory cell is 115 It is as follows.

Therefore, the impurity concentration of the P-type well 10 where the memory cell matrix is formed is set to
The impurity concentration of the fi well IL/11 can be lowered.

Incidentally, in the above embodiment, the case where an N-type substrate is used has been described, but it goes without saying that a P-type substrate may also be used.

〔Effect of the invention〕

As explained above, according to the present invention, the impurity concentration of the second conductivity type well in which the memory cell matrix is formed is lower than the impurity concentration of the second conductivity type well in which peripheral circuits other than the memory cell matrix are formed. As a result, a CMOS memory device that can operate at high speed without deteriorating its resistance to latch-up can be obtained.

[Brief explanation of drawings]

Fig. 1 is a plan view of an embodiment of the present invention, Fig. 2 is a plan view of a conventional C
FIG. 3 is a plan view of the MOS memory device, and FIG. 41 is a cross-sectional view of the CMOS memory device for explaining the latch-up phenomenon.
FIG. 4 is an equivalent circuit diagram of the CMOS memory device shown in FIG. 3; 10.20... P-type well in which memory cell matrix is formed, 11.21... P-type well in which peripheral circuit is formed, 12.22...
・N-type substrate on which peripheral circuits are formed, 30...
・N-type substrate, 31...P-type well, 328,3
2D...P channel MO8FET Sonis,
Drain diffusion layer, 31), 33D... Source and drain diffusion layer of N-channel MO8FET, 34.
...Gate oxide film, 35...Gate electrode, 36...Substrate contact, 37...
Well contact, 38... Input terminal, 39.
...Output terminal, 40...Substrate resistance, 41
...Well resistance %42...The source diffusion layer of N-channel MO8FET is the emitter, and the P-type well is the base. NPN bipolar transistor with N-type substrate as collector, 43... PNP bipolar transistor with source diffusion layer of P-channel transistor as emitter, N-type substrate as base, P well as collector, 44.
...Resistance that expresses leakage current isometrically, 50...
···power supply. Agent Patent Attorney Susumu Uchihara 1''' 1st figure 2 3rd half 4th figure

Claims (1)

[Claims] In a CMOS memory device, a well of a second conductivity type is formed in a semiconductor substrate of a first conductivity type, and a memory cell matrix and a peripheral circuit are formed in the well of the second conductivity type,
A CMOS memory device characterized in that the impurity concentration of the second conductivity type well in which the memory cell matrix is formed is lower than the impurity concentration in the second conductivity type well in which the peripheral circuit is formed.