JPH06188380A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent electrostatic failures of an electrostatic failure prevention circuit and also prevent erroneous operations of a plurality of input stage circuits or a plurality of output stage circuits by inserting a series. resistance element in a connection path for power supply wiring. CONSTITUTION:A drain region or a source region is connected to a connection path between an external terminal for input and an input stage circuit or to a connection path between an external terminal 3P for output and an output stage circuit I/O. The source region or drain region is equipped with a clamping MISFETQn of an electrostatic failure prevention circuit PC connected to an external terminal 3P for power supply. In such a semiconductor integrated circuit device, the source region or drain region of the clamping MISFETQn of the electrostatic failure prevention circuit PC is connected to the external terminal 3P for power supply with power supply wiring 19. A resistance element 18 formed by a material having a high value of specific resistance compared to the material of electric power wiring is inserted and electrically connected in series.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to at least a power supply external terminal connected to an electrostatic breakdown prevention circuit, or a power supply external terminal connected to an input stage circuit or an output stage circuit. And a semiconductor integrated circuit device.

[0002]

BACKGROUND OF THE INVENTION Applicant No. Hei 4-20175 filed previously by as disclosed in (filing date 1992 February 5), SRAM (S tatic R andom A ccess M em
ory) currently has a large capacity of 4 [Mbit]. In this type of SRAM, the electrostatic breakdown prevention circuit is inserted in both the connection path between the input external terminal (bonding pad) and the input stage circuit and the connection path between the output external terminal and the output stage circuit. .

The electrostatic breakdown prevention circuit is provided on the input stage circuit side,
The clamp MOSFET is provided as one protection element regardless of the arrangement on the output stage circuit side. The clamp MOSFET clamps an excessive voltage, which is input to the input external terminal or the output external terminal and causes electrostatic breakdown, by a reverse breakdown phenomenon having a recoverability. This clamp MOSFET is used for the dielectric breakdown of the gate insulating film of the MOSFET of the input stage circuit or the output stage circuit and pn
It is possible to prevent the joint from breaking at the joint.

In the case of the n-channel conductivity type of the clamp MOSFET, the drain region is connected to a connection path between the external input terminal and the input stage circuit and a connection path between the external output terminal and the output stage circuit. The source region is connected to the power supply external terminal. A reference power source (ground voltage 0 [V]) is applied to the power source external terminal, and the power source external terminal is directly connected to the source region of the clamping MOSFET through a power source wiring mainly made of aluminum alloy. . Generally, for the power supply wiring, one having the smallest resistance value is used among the wiring materials used for the SRAM in order to quickly absorb the power supply noise.

Further, the power supply wiring is not only connected to an electrostatic breakdown prevention circuit, but is also branched from an external terminal for power supply as a plurality of power supply wirings, and the branched power supply wirings are connected to a plurality of input stage circuits and a plurality of outputs. Connected to the stage circuit. Normal,
The output stage circuit has a large driving capability, and noise is likely to occur in the power supply wiring, and this noise induces a malfunction of the circuit operation of the input stage circuit. Therefore, the power supply wiring and the power supply external terminal connected to the output stage circuit, and the power supply wiring and the power supply external terminal connected to the input stage circuit are configured as independent separate systems.

[0006]

In the SRAM described above, a general electrostatic breakdown test for inspecting permanent breakdown due to discharge of static electricity is performed by applying a high voltage to a plurality of signal external terminals. However, most of the electrostatic breakdown modes that actually occur in the market usage environment are SR
This is caused by a local potential difference transiently generated inside the SRAM when the electric charge charged in the package that seals and protects the AM (semiconductor pellet) is discharged. As a method for quantitatively evaluating this electrostatic breakdown, a package charging method (device charging method: CD charging method) in which the entire package is charged and discharged from an external terminal to generate a potential difference inside the SRAM.
Law) is proposed. In this package charging method, when discharge starts from the external power supply terminal, an excessive voltage is applied from the external power supply terminal directly to the source region of the clamp MOSFET of the electrostatic discharge protection circuit through the power supply wiring with a small resistance value, instantaneously. To be done. Therefore, dielectric breakdown occurs in the gate insulating film of the clamp MOSFET of the electrostatic breakdown prevention circuit, and junction breakdown of the pn junction between the source region and the substrate occurs, resulting in permanent breakdown of the electrostatic breakdown prevention circuit. It

Further, the arrangement position of the external terminals for the power supply of the SRAM is close to the arrangement position of the power supply leads of the standardized package for the main purpose of absorbing noise, and is located at the arrangement position of the power supply leads. Be regulated. As a result, SR
In the AM, the lengths of the connection paths from the power supply external terminal to each of the plurality of input stage circuits or the connection paths from the power supply external terminal to each of the plurality of output stage circuits are different.
Even if the main layer is made of an aluminum alloy having the smallest resistance value among the wiring materials used in the SRAM as the power supply wiring, the resistance value of the connection path changes if the length of the connection path is different. In particular, since the driving capability of the output stage circuit is larger than that of the input stage circuit, noise generated in the power supply wiring is large due to the circuit operation of the output stage circuit. For this reason, in particular, in a plurality of output stage circuits, the power supply level recovery time differs depending on the length of the connection path to the power supply external terminal, and the circuit operation of the output stage circuit is performed in a state where the power supply level is not recovered. If it is executed, a malfunction will occur.

The objects of the present invention are as follows. (1) In the semiconductor integrated circuit device in which the protection element of the electrostatic breakdown prevention circuit is connected to the power supply external terminal, the electrostatic breakdown of the electrostatic breakdown prevention circuit is prevented.

(2) In a semiconductor integrated circuit device in which a plurality of input stage circuits or a plurality of output stage circuits are connected to a power supply wiring branched from an external power supply terminal, the plurality of input stage circuits or the plurality of output stage circuits are provided. Prevent malfunction of.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) The drain region or the source region is connected to the connection path between the input external terminal and the input stage circuit or the connection path between the output external terminal and the output stage circuit, and the source region or MI for clamp of electrostatic breakdown prevention circuit whose drain area is connected to external terminal for power supply
In a semiconductor integrated circuit device including an SFET, a first portion is provided between the source region or the drain region of the clamping MISFET of the electrostatic breakdown prevention circuit and the power supply external terminal.
While being connected by power supply wiring made of wiring material,
A resistance element formed of a second wiring material having a higher specific resistance value than that of the first wiring material is electrically connected in series and inserted into the connection path of the power supply wiring. The power supply wiring is composed of a single layer of aluminum or an aluminum alloy or a laminated layer having the aluminum or aluminum alloy as a main layer, and the resistance element is composed of a single layer of tungsten arranged in another conductive layer with respect to the power supply wiring.

(2) One of the first power supply wirings branched from the power supply external terminal is connected to the first input stage circuit or the first output stage circuit, and is branched from the power supply external terminal and the first A semiconductor integrated circuit device in which another second power supply wiring formed in the same conductive layer as the power supply wiring is connected to a second input stage circuit or a second output stage circuit, wherein the first power supply wiring and the second power supply wiring are provided. Of these, a resistance element that makes the resistance value of this one connection path substantially equal to the resistance value of the other connection path on the longer connection path side is electrically inserted in one connection path on the shorter connection path side in series. To do.

[0014]

According to the above-mentioned means (1), when an excessive voltage is applied to the external terminal for the power source (when the electrostatic breakdown voltage test based on the package charging method or the device charging method is performed), the power supply wiring Since the excessive voltage propagating through the connection path can be blunted by the resistance element, and the voltage applied instantaneously between the source or drain region and the gate electrode of the clamp MISFET of the electrostatic breakdown prevention circuit can be dispersed (or relaxed). In particular, the breakdown of the gate insulating film of the clamp MISFET and the breakdown of the pn junction can be prevented, the breakdown of the electrostatic breakdown prevention circuit can be prevented, and the breakdown voltage of the semiconductor integrated circuit device can be improved.

According to the above-mentioned means (2), the power supply level supplied to the first input stage circuit and the second input stage circuit, or the power supply level supplied to the first output stage circuit and the second output stage circuit, respectively. Since the recovery time for the noise of the power supply level (power supply fluctuation) can be made uniform and the respective circuit operation timings can be made uniform, the circuit operations can be executed in order and the malfunction of the circuit operation of the semiconductor integrated circuit device can be prevented. .

The structure of the present invention will be described below in 4 [Mbi
An example in which the present invention is applied to an SRAM having a large capacity [t] will be described.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0018]

First, the structure of a package for encapsulating and protecting an SRAM according to an embodiment of the present invention will be described with reference to FIG. 1 (layout diagram).

As shown in FIG. 1, an SRAM (semiconductor pellet) 3 is sealed and protected by a resin package 1. The SRAM 3 has a rectangular planar shape (the shape of the element formation surface), and the resin package 1 has a rectangular shape similar to the planar shape of the SRAM 3.

The SRAM 3 is mounted on the surface of the tab 2B having a rectangular planar shape. The tab 2B has two rectangular short sides (the right side and the left side in FIG. 1) facing each other.
In, the tab suspension leads 2A are integrally connected. In the regions (the upper side and the lower side in FIG. 1) along each of the two long sides of the SRAM 3 which face each other in a rectangular shape,
A plurality of leads (including an internal lead and an external lead) 2C are arranged respectively.

The plurality of leads 2C are numbered according to the standard, and the signals to be applied and the power supply are determined. The SRAM 3 of this embodiment has a large storage capacity of 4 [Mbit], and the resin package 1 has 32 leads 2C arranged therein. In FIG. 1, the 1st lead, 2nd lead, ..., 16th lead are arranged from the left end to the right end along the rectangular lower long side of the SRAM 3. Lead No. 17, lead No. 18, lead No. 32, and lead No. 32 are arranged from the right end to the left end along the upper long side of the rectangular shape.

The first read (2C) is the address signal 1
The 8th and 2nd reads are the address signal 16, the 3rd read is the address signal 14, the 4th read is the address signal 12, the 5th read is the address signal 7, and the 6th read is the address signal 6.
The 7th read is the address signal 5, the 8th read is the address signal 4, the 9th read is the address signal 3, the 10th read is the address signal 2, the 11th read is the address signal 1, and the 12th read is the address signal 0. The lead is input / output signal 0, the 14th lead is input / output signal 1, the 15th lead is input / output signal 2, and the 16th lead is reference power supply Vss. Reference power supply V
ss is the ground power source of the circuit, for example, 0 [V].

The 17th lead is the input / output signal 3, the 18th lead is the input / output signal 4, and the 19th lead is the input / output signal 5 and 20.
The No. read is the input / output signal 6, the No. 21 read is the input / output signal 7, the No. 22 read is the chip select signal, the No. 23 read is the address signal 10, and the No. 24 read is the output enable signal. The 25th read is the address signal 11, the 26th read is the address signal 9, the 27th read is the address signal 8, the 28th read is the address signal 13, the 29th read is the write enable signal, and the 30th read is the address signal 1.
The 7th and 31st leads are the address signal 15, and the 32nd leads are the operating power supply Vcc. The operating power supply Vcc is the operating power supply voltage of the circuit, for example, 5 [V].

Each of the plurality of leads 2C is an SRAM.
3 is electrically connected to each of the plurality of external terminals 3P arranged in the peripheral region of the element forming surface. This electrical connection is made via the wire 4. Each of the plurality of external terminals 3P is arranged at a position close to the lead 2C to be connected.

The 16th lead, that is, the lead 2C to which the reference power source Vss is applied and the external terminal 3P for the reference power source are
In FIG. 1, it is arranged at the right end and the lower end. In this embodiment, three reference power source external terminals 3P are arranged. 1
The one external terminal 3P for reference power supply is connected to the input stage circuit, the output stage circuit, and the electrostatic breakdown prevention circuit, and the other two external terminals 3P for reference power supply are internal circuits (memory cell array,
Direct peripheral circuit, indirect peripheral circuit, etc.).

The 32nd lead, that is, the lead 2C to which the operating power source Vcc is applied and the operating power source external terminal 3P are
In FIG. 1, it is arranged at the left end and the upper end. Three external terminals for operating power supply 3P are similarly arranged in this embodiment. One operating power supply external terminal 3P is connected to the input stage circuit, the output stage circuit, and the electrostatic breakdown prevention circuit, and the other two operating power supply external terminals 3P are connected to the internal circuit.

Internal leads of the SRAM 3, the tab 2B, the tab suspension lead 2A and the lead 2C are sealed with a resin sealing body 5. The resin sealing body 5 is molded by a transfer molding method and, for example, an epoxy resin is used.

The external lead of the lead 2C is molded into a surface mount type or a pin insertion type.

External terminal 3 for the reference power source of the SRAM 3
P, reference power wiring (19) and output stage circuit (I / O)
2 will be described with reference to FIG. 2 (schematic layout diagram).

As shown in FIG. 2, one of the three reference power source external terminals 3P is arranged, and one of the reference power source external terminals 3P is provided.
In FIG. 2, P is the reference power supply wiring 19 extending upward along the right short side of the SRAM 3, and the reference power supply wiring 19 extending downward along the right short side. Branched to. The former reference power supply wiring 19 further extends along the upper long side and is connected to each of the output stage circuits I / O3 to I / O7 arranged along the upper long side. The former reference power supply wiring 19 is an output stage circuit I / O3 to I / O7.
Of the reference power source Vss
To supply. The latter reference power supply wiring 19 further extends along the lower long side and is connected to each of the output stage circuits I / O0 to I / O2 arranged along the lower long side. The latter reference power supply line 19 is connected to the output stage circuits I / O0 to I / O2.
Of the reference power source Vss
To supply.

As shown in FIG. 2, the reference power source external terminal 3P is connected to each of the output stage circuits I / O3 to I / O7 by a reference power source wiring 19 which has a connecting path. It is longer than the connection path of the reference power supply wiring 19 that connects 3P and each of the output stage circuits I / O0 to I / O2. The difference in the length of this connection path is the external terminal 3 for the reference power source.
As described above, P is arranged at a position close to the lead (16th lead) 2C to which the reference power source Vss is applied, and is regulated by the arrangement position of the lead 2C.
It is located on the right side edge and the lower side edge of the
It corresponds to the length of the short side on the right side of 3.

In the connection path of the reference power supply wiring 19 for connecting the external terminal 3P for the reference power supply and each of the output stage circuits I / O0 to I / O2, that is, to the connection path on the side where the connection path is short, as shown in FIG. As shown, the resistance element (R) 18 is inserted. The resistance element 18 will be described later in detail in terms of its planar structure and sectional structure, and is electrically inserted in series in the connection path of the reference power supply wiring 19.

When an excessive voltage for inducing electrostatic discharge is applied to the external terminal 3P for the reference power source, the resistance element 18 dulls the excessive voltage, and the output stage circuits I / O0-I0.
It is configured for the purpose of preventing electrostatic breakdown of the protection elements of the respective electrostatic breakdown prevention circuits of / O2. SRAM of this embodiment
3, the resistor element 18 is connected to the reference power source external terminal 3P and each of the output stage circuits I / O3 to I / O7 in the connection route of the reference power source wiring 19, that is, the connection route on the longer side. Not inserted. The connection path on the longer connection path has a larger parasitic resistance value as the connection path is longer, and the total resistance obtained by adding the resistance value of the resistance element 18 to the resistance value on the connection path on the shorter connection path side. Since it is equal to the value, the resistance element 18 is basically not inserted.

The resistance element 18 can substantially match the resistance value of the connection path on the long side of the connection path with the resistance value of the connection path on the short side of the connection path. That is, the resistance element 18 is connected to the output stage circuit I / from the external terminal 3P for the reference power source.
The connection path between O0 and I / O2 increases the resistance value of the connection path on the short side, and the connection between the external terminal 3P for the reference power source and each of the output stage circuits I / O3 to I / O7 It can be set equal to the resistance value of the connection path on the longer side. Therefore, in each of the output stage circuits I / O0 to I / O2 and each of the output stage circuits I / O3 to I / O7,
When noise occurs in the reference power supply Vss, the recovery time of the power supply level can be made uniform.

The resistance value R of the resistance element 18 is such that the length of the connection path on the shorter connection path side is L1, the length of the connection path on the longer connection path side is L2, and the wiring width of the reference power supply wiring 19 is set. If W and the specific resistance of the reference power supply line 19 are ρ, the calculation can be performed by the following equation 1.

[0036]

[Equation 1]

When the resistance value R of an example of the resistance element 18 is calculated with concrete numerical values, the connection path length L1 is 800
[Μm], the connection path length L2 is 5000 [μm], the wiring width W of the reference power supply wiring 19 is 40 [μm], and the specific resistance ρ of the reference power supply wiring (wiring whose main layer is an aluminum alloy) 19 is When it is set to 0.5 [Ω / □], the resistance value R of the resistance element 18 becomes about 50 [Ω].

Next, the output stage circuit I / O of the SRAM 3
The specific circuit configuration of the electrostatic breakdown prevention circuit PC will be described with reference to FIG. 3 (circuit diagram).

As shown in FIG. 3, the output stage circuit I / O is
It is composed of MISFETs Qn1 and Qn2 as the final output stage and preceding logic circuits L1 and L2.

MISFET Qn1 as the final output stage,
Each of Qn2 is of n-channel conductivity type. Drain region of MISFET Qn1, MISFET
Each of the source regions of Qn2 is connected to the data output signal external terminal 3P. The source region of MISFETQn1 is connected to the reference power source Vss, and MISFETQn
The second drain region is connected to the operating power supply Vcc. The reference power supply Vss is supplied from the reference power supply external terminal 3P through the reference power supply wiring 19. Similarly, the operating power supply Vcc is supplied from the operating power supply external terminal 3P through the operating power supply wiring 19.

The gate electrode of the MISFET Qn1 as the final output stage is controlled by the preceding logic circuit L1, and this preceding logic circuit L1 is connected to the data output signal terminal P1 and the output control signal terminal P3, respectively. MISFETQn
The second gate electrode is controlled by the preceding logic circuit L2, and this preceding logic circuit L2 is connected to each of the inverted data output signal terminal P2 and the output control signal terminal P3.

The electrostatic breakdown prevention circuit PC is inserted in the connection path between the output stage circuit I / O and the data output signal external terminal 3P. This electrostatic breakdown prevention circuit PC is composed of two clamp MISFETs Qn3 and Qn4 electrically connected in parallel to the connection path. Each of the clamp MISFETs Qn3 and Qn4 is of n-channel conductivity type. MISFE for clamp
Each of the source region and the gate electrode of TQn3 has a reference power source V
The drain region is connected to the connection path. The source region of the clamp MISFET Qn4 is connected to the connection path, the gate electrode is connected to the reference power supply Vss, and the drain region is connected to the operating power supply Vcc. The reference power supply Vss is supplied from the reference power supply external terminal 3P through the reference power supply wiring 19. Similarly, the operating power supply Vcc is supplied from the operating power supply external terminal 3P to the operating power supply wiring 1
Supplied through 9.

Next, a specific cross-sectional structure of the resistance element (R) 18 inserted in the connection path from the external terminal 3P for the reference power source to the electrostatic breakdown prevention circuit PC and the output stage circuit I / O. The planar structure will be described with reference to FIG. 4 (sectional view) and FIG. 5 (plan view) together with the sectional structure of the memory cell of the SRAM 3.

First, as shown in FIG. 4, the SRAM 3 is mainly composed of a p-type semiconductor substrate 10 made of single crystal silicon. The SRAM 3 is mainly composed of complementary MISFETs, a p-type well region 11 is formed in a part of the p-type semiconductor substrate 10, and n is not shown in the other part of the region.
A mold well region is constructed. An element isolation insulating film 12 is formed on the main surface of each inactive region of the p-type well region 11 and the n-type well region.

The memory cell of the SRAM 3 has a total of 6-layer wiring structure including four gate wiring layers and two wiring layers. The memory cell is composed of two transfer MISFETs and a flip-flop circuit as an information storage unit. The flip-flop circuit is composed of two driving MISFETs and two load MISFETs.

The driving MISFET of the memory cell is mainly composed of the gate electrode 13 formed of the first gate wiring layer and the n-type semiconductor region 15 used as a source region and a drain region. Gate electrode 1
3 is formed of, for example, a polycrystalline silicon film. MISF for transfer
ET is used as the gate electrode 14 formed in the second-layer gate wiring layer and the source and drain regions.
The type semiconductor region 15 is used as a main constituent element. The gate electrode 14 is also used as a word line, and is formed of, for example, a laminated film including a polycrystalline silicon film and a WSi film laminated on the polycrystalline silicon film. The load MISFET has an SOI structure or a TFT structure, and has a source region, a channel forming region, and a drain formed by the gate electrode 16 formed by the third gate wiring layer and the fourth gate wiring layer. The area 17 is configured as a main component. Both the gate electrode 16 and the source region 17 are formed of a polycrystalline silicon film.

In the upper layer of the memory cell, the intermediate wiring 18 formed in the first wiring layer, the main word line 18 and the sub word line 18 not shown, and the data line formed in the second wiring layer. Each of the nineteen is constructed. The intermediate conductive layer 18 and the like are formed of, for example, a W film, and the W film has a thickness of about 5 mm.
It has a specific resistance value of [Ω / □]. In addition, the intermediate conductive layer 18
For example, a refractory metal film other than the W film may be used. The data line 19 is composed of, for example, a single layer of an aluminum alloy film (to which at least one of Si and Cu is added), or a laminated layer in which barrier metal films are stacked with the aluminum alloy film as a main layer. A pure aluminum film may be used as the data line 19. The aluminum alloy film has a specific resistance value which is smaller than that of the W film by about one digit, and has a specific resistance value of about 0.5 [Ω / □].

An interlayer insulating film 20 is formed between each of the four gate wiring layers and between each of the two wiring layers, and a final protective film 20 is formed above the data line 19.

External terminal 13 for the reference power source of the SRAM 3
All external terminals including P, 13P, reference power supply wiring 1
9. Each of the operating power supply wirings 19 is formed by the fourth wiring layer formed in the same wiring layer as the data line 19.
The resistance element (R) 18 inserted in the connection path of the reference power supply line 19 is formed of a third wiring layer formed in the same wiring layer as the intermediate conductive layer 18 and the like. The reference power supply line 19 and the resistance element 18 are electrically connected to each other through a connection hole TH formed in the interlayer insulating film 20. In the SRAM 3 of this embodiment, the resistance element 18 has about 30 to 50.
Set to [Ω].

In this way, the drain region is connected to the connection path between the output signal external terminal 13P and the output stage circuit I / O, and the source region is connected to the reference power supply external terminal 13P to prevent electrostatic breakdown. MIS for clamping circuit CP
In the SRAM 3 including the FET Qn3, the reference power supply wiring 1 formed by using an aluminum alloy material as a main layer between the source region of the clamping MISFET Qn3 of the electrostatic breakdown prevention circuit CP and the external terminal 13P for the reference power supply.
9 and the resistance element (R) 18 made of a W material having a higher specific resistance value than the aluminum alloy material is electrically connected in series in the connection path of the reference power supply wiring 19. Is inserted.

With this configuration, when an excessive voltage is applied to the external terminal 13P for the reference power source (when an electrostatic breakdown voltage test based on the package charging method or the device charging method is performed), the wiring of the reference power source wiring 19 is connected. The excessive voltage propagating through the path can be blunted by the resistance element 18, and the MISFET Qn3 for clamping of the electrostatic discharge protection circuit CP can be clamped.
Since it is possible to disperse (or relax) the voltage applied instantaneously between the source region and the gate electrode of the
It is possible to prevent the dielectric breakdown of the gate insulating film of TQn3, the junction breakdown of the pn junction, the electrostatic breakdown prevention circuit CP, and the breakdown voltage of the SRAM3. Similarly, the MISFET for clamping of the electrostatic breakdown prevention circuit CP
It is possible to prevent dielectric breakdown of the gate insulating film of Qn4 and junction breakdown of the pn junction.

Further, one reference power supply wiring 19 branched from the reference power supply external terminal 13P is connected to the output stage circuit I / O, and is branched from the reference power supply external terminal 13P and the one reference In the SRAM 3 in which the other one reference power supply wiring 19 formed in the same conductive layer as the power supply wiring 19 is connected to another output stage circuit I / O, the one reference power supply wiring 19 and the other one Among the reference power supply wirings 19, one of the connection paths on the shorter connection path is
A resistance element (R) 1 that makes the resistance value of the one connection path substantially match the resistance value of the other connection path on the longer connection path side.
8 is electrically inserted in series.

With this configuration, the output stage circuit I / O,
Since it is possible to make the recovery time for the noise (power fluctuation) of the reference power supply level supplied to each of the other output stage circuit I / O uniform and to make the respective circuit operation timing uniform, it is possible to execute the circuit operations in order. , The malfunction of the circuit operation of the SRAM 3 can be prevented.

As described above, the inventions made by the present inventor are
Although the specific description has been given based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

For example, according to the present invention, a resistance element inserted in series and a MISFET for clamping inserted in parallel in a connection path between an external terminal for an input signal and an input stage circuit.
In the semiconductor integrated circuit device in which the electrostatic breakdown prevention circuit having the above is arranged, a resistance element is inserted in the connection path of the reference power supply wiring between the source region of the clamping MISFET of the electrostatic breakdown prevention circuit and the external terminal for the reference power supply. You may.

The present invention is not limited to SRAM,
DRAM (D ynamic RAM) semiconductor memory circuit device, a semiconductor logic integrated circuit device or the like, such as, can be widely applied to a semiconductor integrated circuit device.

[0057]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

In the semiconductor integrated circuit device in which the protection element of the electrostatic breakdown prevention circuit is connected to the power supply external terminal, the electrostatic breakdown of the electrostatic breakdown prevention circuit can be prevented.

Further, in a semiconductor integrated circuit device in which a plurality of input stage circuits or a plurality of output stage circuits are connected to a power supply wiring branched from an external terminal for power supply, in the plurality of input stage circuits or the plurality of output stage circuits, Malfunctions can be prevented.

[Brief description of drawings]

FIG. 1 is a layout diagram of an SRAM package according to an embodiment of the present invention.

FIG. 2 is a schematic layout diagram of an external terminal of the SRAM, a power supply wiring, and an output stage circuit.

FIG. 3 is a circuit diagram of an output stage circuit of the SRAM 3 and an electrostatic breakdown prevention circuit.

FIG. 4 is a sectional view of a main part of the SRAM.

FIG. 5 is a plan view of a main part of the SRAM.

[Explanation of symbols]

13P ... External terminal, 18, R ... Resistor element, 19 ... Power supply wiring, I / O ... Output stage circuit, CP ... Electrostatic breakdown prevention circuit,
Qn ... MISFET.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Shigeru Honjo 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Musashi Factory, Hitachi, Ltd. (72) Inventor Kazutomo Ogura, Kodaira, Tokyo 5-20-1 Honcho, Ltd. Musashi Factory, Hitachi, Ltd. (72) Inventor Hideaki Nakamura 5-20-1 Josuihoncho, Kodaira-shi, Tokyo Hirate Super L.S.I. Engineering Co., Ltd. (72 ) Inventor Mitsui alone 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Inside Hiritsu Cho-LS Engineering Co., Ltd.

Claims (3)

[Claims] 1. A drain region or a source region is connected to a connection path between an input external terminal and an input stage circuit, or a connection path between an output external terminal and an output stage circuit, and a source region or a drain. MISFE for clamping of electrostatic breakdown prevention circuit whose area is connected to external terminal for power supply
In the semiconductor integrated circuit device including T, the source region or the drain region of the clamping MISFET of the electrostatic breakdown prevention circuit and the power supply external terminal are connected by a power supply wiring formed of a first wiring material, and A semiconductor integrated device characterized in that a resistance element formed of a second wiring material having a higher specific resistance value than that of the first wiring material is electrically connected in series in the connection path of the power supply wiring. Circuit device. 2. The power supply wiring according to claim 1 is composed of a single layer of aluminum or an aluminum alloy or a laminated layer having the main layer as a main layer, and the resistance element is formed on another conductive layer with respect to the power supply wiring. A semiconductor integrated circuit device comprising a single layer of tungsten arranged. 3. The first power supply wiring branched from the power supply external terminal is connected to a first input stage circuit or a first output stage circuit, and is branched from the power supply external terminal and the first power supply. In the semiconductor integrated circuit device in which the other one second power supply wiring formed in the same conductive layer as the wiring is connected to the second input stage circuit or the second output stage circuit, the first power supply wiring and the second power supply wiring are Among them, a resistance element that makes the resistance value of this one connection path substantially equal to the resistance value of the other connection path on the long connection path side is electrically inserted in series to one connection path on the shorter connection path side. A semiconductor integrated circuit device characterized by the above.