JPS6334496B2 - - Google Patents
Info
- Publication number
- JPS6334496B2 JPS6334496B2 JP58166910A JP16691083A JPS6334496B2 JP S6334496 B2 JPS6334496 B2 JP S6334496B2 JP 58166910 A JP58166910 A JP 58166910A JP 16691083 A JP16691083 A JP 16691083A JP S6334496 B2 JPS6334496 B2 JP S6334496B2
- Authority
- JP
- Japan
- Prior art keywords
- channel
- data
- main memory
- chb
- access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58166910A JPS6063652A (ja) | 1983-09-10 | 1983-09-10 | チヤネルバツフア制御方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58166910A JPS6063652A (ja) | 1983-09-10 | 1983-09-10 | チヤネルバツフア制御方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6063652A JPS6063652A (ja) | 1985-04-12 |
JPS6334496B2 true JPS6334496B2 (enrdf_load_stackoverflow) | 1988-07-11 |
Family
ID=15839903
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58166910A Granted JPS6063652A (ja) | 1983-09-10 | 1983-09-10 | チヤネルバツフア制御方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6063652A (enrdf_load_stackoverflow) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3561670B2 (ja) * | 1999-12-17 | 2004-09-02 | 三洋電機株式会社 | メモリ制御回路 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5242032A (en) * | 1975-09-29 | 1977-04-01 | Hitachi Ltd | Data processing unit |
JPS5720588A (en) * | 1980-07-10 | 1982-02-03 | Matsushita Seiko Co Ltd | Head oscillator for electrical fan |
-
1983
- 1983-09-10 JP JP58166910A patent/JPS6063652A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6063652A (ja) | 1985-04-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5247648A (en) | Maintaining data coherency between a central cache, an I/O cache and a memory | |
US4736293A (en) | Interleaved set-associative memory | |
US5263142A (en) | Input/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devices | |
CA1187198A (en) | System for controlling access to channel buffers | |
JPS6015760A (ja) | Dasdキヤツシユの情報をステ−ジングするための方法 | |
EP0533427B1 (en) | Computer memory control system | |
US6026032A (en) | High speed data buffer using a virtual first-in-first-out register | |
JPS6334496B2 (enrdf_load_stackoverflow) | ||
JP2580263B2 (ja) | バッファ記憶装置 | |
KR100251784B1 (ko) | 캐쉬 메모리 컨트롤러 및 이를 제공하는 방법 | |
USRE38514E1 (en) | System for and method of efficiently controlling memory accesses in a multiprocessor computer system | |
JPS6329297B2 (enrdf_load_stackoverflow) | ||
JPS59218692A (ja) | ロジカルバツフア記憶制御方式 | |
JPS6055859B2 (ja) | チャネル・バッファ制御方式 | |
JPS6022777B2 (ja) | デ−タ転送方式 | |
JP2963257B2 (ja) | 処理装置 | |
JPH0211931B2 (enrdf_load_stackoverflow) | ||
JPS6045872A (ja) | 高速緩衝記憶装置 | |
JPS61173355A (ja) | デイスクキヤツシユ設置方式 | |
JP2001229074A (ja) | メモリ制御装置と情報処理装置及びメモリ制御チップ | |
CA2036372C (en) | An input/output cache for caching direct (virtual) memory access data | |
CA2030888C (en) | Cache data consistency mechanism for workstations and servers with an i/o cache | |
JPS60140444A (ja) | 共有メモリに対する部分書込みの制御方法 | |
JPH03271859A (ja) | 情報処理装置 | |
JPH0689228A (ja) | キャッシュメモリ制御装置 |