JPS6332998A - Multilayer printed interconnection board - Google Patents

Multilayer printed interconnection board

Info

Publication number
JPS6332998A
JPS6332998A JP17650686A JP17650686A JPS6332998A JP S6332998 A JPS6332998 A JP S6332998A JP 17650686 A JP17650686 A JP 17650686A JP 17650686 A JP17650686 A JP 17650686A JP S6332998 A JPS6332998 A JP S6332998A
Authority
JP
Japan
Prior art keywords
multilayer printed
pattern
signal pattern
inner layer
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17650686A
Other languages
Japanese (ja)
Inventor
晃一 小川
池田 明雄
敏弘 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17650686A priority Critical patent/JPS6332998A/en
Publication of JPS6332998A publication Critical patent/JPS6332998A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔概要〕 多層印刷配線基板の内層基板でシールドを要する信号パ
ターン(例えば同−丁妖面に低電圧レベルの信号パター
ン中に混在する高電圧レベルの信号パターン又はその逆
の場合)をシールドする溝造であって、シールドを要す
る信号パターンの周囲に線状の接地パターンを形成し、
該信号パターンを形成した内層基板に隣接する他の対応
面に、線状の接地パターンと外形の同じ板状接地パター
ンを形成して、他の信号パターンの影響を防止するので
動作が安定し、信頼度が向上する。
[Detailed Description of the Invention] [Summary] A signal pattern that requires shielding on an inner layer board of a multilayer printed wiring board (for example, a signal pattern of a high voltage level mixed in a signal pattern of a low voltage level, or vice versa) A linear ground pattern is formed around the signal pattern that requires shielding.
A plate-shaped ground pattern having the same outer shape as the linear ground pattern is formed on another corresponding surface adjacent to the inner layer substrate on which the signal pattern is formed, thereby preventing the influence of other signal patterns, resulting in stable operation. Improves reliability.

〔産業上の利用分野〕[Industrial application field]

本発明は、内層基板に形成した特定の信号パターンにシ
ールドを施した多層印刷配線基板に関する。
The present invention relates to a multilayer printed wiring board in which a specific signal pattern formed on an inner layer board is shielded.

電子部品は高集積化技術の進展7.と伴ない小形。7. Advances in highly integrated technology for electronic components. Accompanying small size.

高密度化され、これら電子部品を実装する印刷配線基板
は、各種電子機器を構成するユニットとして多用されて
いるが、さらに電子装置の小形、軽量化の要望により複
数枚の基板を稽層した多層印刷配線基板が出現し、同層
板上に異種の信号パターンを混在せしめている。
High-density printed wiring boards, on which these electronic components are mounted, are often used as units that make up various electronic devices. With the advent of printed wiring boards, different types of signal patterns are mixed on the same layer board.

〔従来の技術〕[Conventional technology]

従来の多層印刷配線基板の内層基板に形成したシールド
を要する信号パターンのシールドは、該信号パターンを
接地レヘルの配線等で平面的に囲んでいた。
In a conventional shield for a signal pattern that requires a shield, which is formed on an inner layer board of a multilayer printed wiring board, the signal pattern is surrounded in a plane by ground level wiring or the like.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来の多層印刷配線基板にあっては、シールドを要
する信号パターンを平面的にシールドを行なっているが
、立体的にシールドを行なっていないため、他の信号パ
ターンにより電気的(とくに電磁的)な障害を受け、誤
動作を起こし信頼度に難点があるという問題点があった
In the above-mentioned conventional multilayer printed wiring board, signal patterns that require shielding are shielded two-dimensionally, but because they are not shielded three-dimensionally, electrical (especially electromagnetic) The problem was that it was subject to major failures, resulting in malfunctions and low reliability.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、上記の問題点を解決してシールドを要する信
号パターンを平面的および立体的なシールドを行なった
多層印刷配線基板を提供するものである。
The present invention solves the above-mentioned problems and provides a multilayer printed wiring board in which signal patterns requiring shielding are shielded two-dimensionally and three-dimensionally.

すなわち、多層印刷配線基板1における内層基板13の
一部信号パターン2のシールド構造を、この信号パター
ン2の周囲の同一平面上に線状の接地パターン4を形成
し、前記信号パターン2を形成した内層基板13に隣接
する他の内層基板の対応面に、前記接地パターン4と外
形の同じ板状接地パターン5を形成したことによって解
決される。
That is, the shield structure of the partial signal pattern 2 of the inner layer board 13 in the multilayer printed wiring board 1 is formed by forming a linear ground pattern 4 on the same plane around the signal pattern 2 to form the signal pattern 2. This problem is solved by forming a plate-shaped ground pattern 5 having the same external shape as the ground pattern 4 on a corresponding surface of another inner layer substrate adjacent to the inner layer substrate 13.

〔作用〕[Effect]

上記多層印刷配線基板は、各種例えば同一層面に低電圧
レベルの信号パターンと高電圧レヘルの信号パターンが
混在している場合に、その少ない側の信号パターンをシ
ールドして他の信号レベルへの電気(電磁)的障害を防
止して、誤動作をなくし信頼度が向上する。
The above-mentioned multilayer printed wiring board can be used to shield the signal pattern on the side where there is less, for example, when a low voltage level signal pattern and a high voltage level signal pattern coexist on the same layer surface, and provide electricity to other signal levels. (Electromagnetic) interference is prevented, malfunctions are eliminated, and reliability is improved.

〔実施例〕〔Example〕

第1図及び第2図は、本発明の一実施例を説明する図で
、第1図は分解斜視図、第2図は分解側断面図である。
1 and 2 are views for explaining one embodiment of the present invention, with FIG. 1 being an exploded perspective view and FIG. 2 being an exploded side sectional view.

一図において、ガラスエポキシ樹脂等からなる複数(図
面では5枚を示す)の基板1)〜15に、所定のパイヤ
ホール(信号を接続する孔)3を設け、同種のパイ中ホ
ール3間を信号線で接続しているが、例えば同一内層基
板13に異種の信号パターンを形成し、その中でシール
ドを要する信号パターン2のシールドを行なう場合には
、まず前記信号パターン2を線状の接地パターン4で囲
み、同一平面」二の他の信号パターンとのシールドを行
ない、さらに前記信号パターン4を設けた内層基板13
に隣接する内層基板12と14の前記信号パターン4の
対向するそれぞれの面に、前記線状の接地パターン4の
外形と同等もしくは若干大きい形状の板状接地パターン
5を形成したのち、前記内層基板12と13問および1
3と14間の接地パターン4と5の間に、プリプレグ等
の絶縁板6を複数枚介在せしめて接着剤で接着積層する
ものである。
In the figure, predetermined pie holes (holes for connecting signals) 3 are provided on a plurality of (five boards are shown in the drawing) substrates 1) to 15 made of glass epoxy resin, etc., and signals are connected between the same type of pie holes 3. For example, when forming different types of signal patterns on the same inner layer board 13 and shielding the signal pattern 2 that requires shielding, first connect the signal pattern 2 with a linear ground pattern. An inner layer substrate 13 surrounded by 4 and shielded from other signal patterns on the same plane 2, and further provided with the signal pattern 4.
After forming a plate-shaped ground pattern 5 having a shape equal to or slightly larger than the linear ground pattern 4 on each side of the inner layer substrates 12 and 14 facing the signal pattern 4 adjacent to the inner layer substrates 12 and 14, Questions 12 and 13 and 1
A plurality of insulating plates 6 such as prepreg are interposed between the ground patterns 4 and 5 between the ground patterns 3 and 14, and are bonded and laminated with an adhesive.

なお、本実施例では多層印刷配線基板1を5枚積層した
説明をしたが、3枚以上複数枚にも適用が可能である。
In this embodiment, five multilayer printed wiring boards 1 are laminated, but the present invention can also be applied to three or more multilayer printed wiring boards 1.

またシールドを要する信号パターンを基板13に形成し
た説明をしたが、他の内層基板12.14のシールドを
要する信号パターンにも通用できる。
Further, although the explanation has been given in which a signal pattern requiring shielding is formed on the substrate 13, the present invention can also be applied to signal patterns requiring shielding on other inner layer substrates 12 and 14.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように、本発明によればシール
ドを要する信号パターンを平面的、立体的にシールドが
行なえるので、信号パターンへの電磁的妨害が防止でき
、誤動作が解消し信頼度の向上に極めて有効である。
As is clear from the above description, according to the present invention, signal patterns that require shielding can be shielded two-dimensionally or three-dimensionally, so electromagnetic interference to signal patterns can be prevented, malfunctions can be eliminated, and reliability can be improved. It is extremely effective for improvement.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例を説明する分解斜視図。 第2図は、本発明を説明する分解側断面図である。 図において、1は多層印刷配線基板、2はシールドを要
する信号パターン、3はパイヤホール、4は線状の接地
パターン、5ば板状の接地パターン、6は絶縁板、1)
.15は基板、12〜14は内層基板、をそれぞれ示す
。 b 不碇1胸j楚Lqす31分角り便1跡動の第2図
FIG. 1 is an exploded perspective view illustrating an embodiment of the present invention. FIG. 2 is an exploded side sectional view illustrating the present invention. In the figure, 1 is a multilayer printed wiring board, 2 is a signal pattern that requires shielding, 3 is a pie hole, 4 is a linear ground pattern, 5 is a plate-shaped ground pattern, 6 is an insulating plate, 1)
.. Reference numeral 15 indicates a substrate, and 12 to 14 indicate inner layer substrates, respectively. b Fukari 1 Chest J Chu Lqsu 31 minute square flight 1 trace movement 2nd figure

Claims (1)

【特許請求の範囲】  多層印刷配線基板(1)における内層基板(13)の
一部信号パターン(2)のシールド構造を、 前記信号パターン(2)の同一平面上で該信号パターン
(2)の周囲に線状の接地パターン(4)を形成し、前
記信号パターン(2)を形成した内層基板(13)に隣
接する他の内層基板の対応面に、前記接地パターン(4
)と外形の同じ板状接地パターン(5)を形成したこと
を特徴とする多層印刷配線基板。
[Claims] The shield structure of a part of the signal pattern (2) of the inner layer board (13) in the multilayer printed wiring board (1) is provided by forming the shield structure of the signal pattern (2) on the same plane as the signal pattern (2). A linear ground pattern (4) is formed around the periphery, and the ground pattern (4) is placed on the corresponding surface of another inner layer substrate adjacent to the inner layer substrate (13) on which the signal pattern (2) is formed.
) A multilayer printed wiring board characterized in that a plate-like ground pattern (5) having the same outer shape as that of (5) is formed.
JP17650686A 1986-07-25 1986-07-25 Multilayer printed interconnection board Pending JPS6332998A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17650686A JPS6332998A (en) 1986-07-25 1986-07-25 Multilayer printed interconnection board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17650686A JPS6332998A (en) 1986-07-25 1986-07-25 Multilayer printed interconnection board

Publications (1)

Publication Number Publication Date
JPS6332998A true JPS6332998A (en) 1988-02-12

Family

ID=16014827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17650686A Pending JPS6332998A (en) 1986-07-25 1986-07-25 Multilayer printed interconnection board

Country Status (1)

Country Link
JP (1) JPS6332998A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0371661A (en) * 1989-08-11 1991-03-27 Fujitsu Ltd Electronic circuit package and manufacture thereof
JPH0423490A (en) * 1990-05-18 1992-01-27 Nec Corp Multilayer wiring board
JPH04325854A (en) * 1991-04-26 1992-11-16 Hitachi Ltd Polygon mirror motor
JP2003046358A (en) * 2001-05-16 2003-02-14 Matsushita Electric Ind Co Ltd Laminated filter, laminated composite device, and communication device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0371661A (en) * 1989-08-11 1991-03-27 Fujitsu Ltd Electronic circuit package and manufacture thereof
JPH0423490A (en) * 1990-05-18 1992-01-27 Nec Corp Multilayer wiring board
JPH04325854A (en) * 1991-04-26 1992-11-16 Hitachi Ltd Polygon mirror motor
JP2003046358A (en) * 2001-05-16 2003-02-14 Matsushita Electric Ind Co Ltd Laminated filter, laminated composite device, and communication device

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