JPS61253899A - Hybrid ic - Google Patents
Hybrid icInfo
- Publication number
- JPS61253899A JPS61253899A JP9547585A JP9547585A JPS61253899A JP S61253899 A JPS61253899 A JP S61253899A JP 9547585 A JP9547585 A JP 9547585A JP 9547585 A JP9547585 A JP 9547585A JP S61253899 A JPS61253899 A JP S61253899A
- Authority
- JP
- Japan
- Prior art keywords
- circuits
- circuit
- metal plate
- hybrid
- shielding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、二種類の回路間に悪影響を与えることなく高
密度化した混成ＩＣに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a hybrid IC that is highly densified without adversely affecting two types of circuits.
混成ＩＣは、主にアナログ信号を扱う回路に用いられて
いる。然しなから最近では、ディジタル信号を扱う回路
にも用いられるようになり、更にアナログ回路とディジ
タル回路の両方が混在した回路へと発展しつつある。Hybrid ICs are mainly used in circuits that handle analog signals. Recently, however, they have come to be used in circuits that handle digital signals, and are also evolving into circuits that are a mixture of both analog and digital circuits.
このように、アナログ回路とディジタル回路の両方を混
在して、高密度に実装した場合は、ディジタル信号がア
ナログ回路に影響を及ぼし、誤動作を誘発するという技
術的な問題がある。In this way, when both analog circuits and digital circuits are mixed and packaged at high density, there is a technical problem that the digital signals affect the analog circuits, causing malfunctions.
そこで、従来は、上記影響を回避するために、アナログ
回路とディジタル回路Ω二つの混成ＩＣを単に端子によ
って接続していた（実開昭５４−８８６６６号公報）。Therefore, conventionally, in order to avoid the above-mentioned influence, two hybrid ICs consisting of an analog circuit and a digital circuit Ω were simply connected through terminals (Japanese Utility Model Publication No. 54-88666).
然しながら、これらを単に端子で接続しただけでは、双
方の影響を完全に回避したとはいえず、高密度に実装し
た場合は、双方の影響が大きくなり、当該技術分野の発
展に対し大きな障壁になっているのが実情である。However, simply connecting them with terminals does not completely avoid the effects of both, and if they are densely packaged, the effects of both will increase and become a major barrier to the development of this technical field. The reality is that this is the case.
本発明は、上記実情を鑑みてなされたものであり、アナ
ログ回路とディジタル回路のように、相互の信号が互い
に悪影響を及ぼし合５ような回路が混在しても、その影
響をなくシ、かつ、高密度の実装を可能にした混成ＩＣ
を提供せんとするものである。The present invention has been made in view of the above-mentioned circumstances, and even if circuits such as analog circuits and digital circuits in which mutual signals adversely influence each other coexist, the present invention eliminates the influence and eliminates the influence. , hybrid IC that enables high-density packaging
We aim to provide the following.
即ち、本発明は、相互に悪影響を与える回路を別々にす
るために、これら回路を片面にのみ形成した回路基板を
用意し、この回路基枚の回路を形成していない面同志の
間にシールド用金属板を介在して重ね合せ、この重ね合
ぜた回路基板をクリップ形リード端子により挾持して一
体化したものである。That is, in order to separate circuits that adversely affect each other, the present invention prepares a circuit board on which these circuits are formed only on one side, and places a shield between the surfaces of the circuit board on which no circuits are formed. The circuit boards are stacked with a metal plate interposed therebetween, and the stacked circuit boards are held together by clip-type lead terminals and integrated.
以下本発明の一実施例について詳細に説明する０
第１図は、デ二アルインタイプの実施例である。第１図
及び第２図釦おいて、６及び８は、片面にのみ回路を形
成した回路基板であり、例えば、６はアナログ用回路基
板、８は、ディジタル用回路基板である。７は、シール
ド用金属板であり、第３図に示すように、端子７′が形
成されている。上記回路基板６、８は、回路が形成され
ていない面同志の間にシールド用金属板７を介在して重
ね合せられ、クリップ形リード端子５により挾持されて
一体化されている。なお１．２．３、及び４は、回路基
板６．８上に搭載された素子である。An embodiment of the present invention will be described in detail below. FIG. 1 shows a digital inline type embodiment. In the buttons of FIGS. 1 and 2, 6 and 8 are circuit boards having a circuit formed only on one side. For example, 6 is an analog circuit board, and 8 is a digital circuit board. 7 is a metal plate for shielding, and as shown in FIG. 3, terminals 7' are formed. The circuit boards 6 and 8 are stacked on top of each other with a shielding metal plate 7 interposed between the surfaces on which no circuit is formed, and are held together by clip-type lead terminals 5 to be integrated. Note that 1.2.3 and 4 are elements mounted on the circuit board 6.8.
以上のように構成した本実施例において、シールド用金
属板７のリード７′に電源又はグランド等を接続する。In this embodiment configured as described above, the lead 7' of the shielding metal plate 7 is connected to a power source, a ground, or the like.
このようにして、回路基板６及び８相互間の影響がシー
ルド金属板７によって防止される。In this way, the influence between the circuit boards 6 and 8 is prevented by the shield metal plate 7.
次に第４図は、シングルインタイブの実施例である。第
４図及び第５図において、１４及び１６は、片面にのみ
回路を形成した回路基板である。１５は、シールド用金
属板であり、第６図に示すように端子１５′が形成され
ている。上記、回路基板１４．１６は、回路が形成され
ていない面同志の間にシールド用金属板１５を介在して
重ね合され、クリップ形瑞子１３により挾持されて一体
化されている。なお９．１０．１１．１２は、回路基板
１４．１６上に搭載された素子である。Next, FIG. 4 shows an example of a single intival. In FIGS. 4 and 5, 14 and 16 are circuit boards having a circuit formed only on one side. 15 is a metal plate for shielding, and as shown in FIG. 6, terminals 15' are formed. The circuit boards 14 and 16 are stacked on top of each other with a shielding metal plate 15 interposed between the surfaces on which no circuit is formed, and are held together by clip-shaped screws 13 to be integrated. Note that 9.10.11.12 is an element mounted on the circuit board 14.16.
本実施例においても、第１図に示した実施例と同様に、
シールド用金属板１５によって、回路基板１４及び１６
上に形成された混成回路同志の影響が防止される。In this embodiment, similarly to the embodiment shown in FIG.
The circuit boards 14 and 16 are connected by the shielding metal plate 15.
The influence of hybrid circuits formed above is prevented.
なお第７図は、第３図及び第６図に示したシールド用金
属板７又は１５のように、端子７′又は１５′を設けず
に、回路基板１７．１９０間に介在したシールド用金属
板１８とクリップ形リード２０とをはんだ１６により接
続したものであり、同様の効果を有する。Note that FIG. 7 shows a shielding metal plate interposed between circuit boards 17 and 190 without providing terminals 7' or 15' like the shielding metal plate 7 or 15 shown in FIGS. 3 and 6. The plate 18 and the clip-shaped lead 20 are connected by the solder 16, and have the same effect.
又、シールド用金属枚の端子は、−個に限らず、複数設
けてもよい。Further, the number of terminals of the shielding metal sheet is not limited to -, but a plurality of terminals may be provided.
以上詳述した通り、本発明に係る混成ＩＣによれば、片
面にのみ回路を形成した回路基板を用意し、回路を形成
していない面同志の間Ｋ。As detailed above, according to the hybrid IC according to the present invention, a circuit board with a circuit formed only on one side is prepared, and a gap K between the surfaces on which no circuit is formed is provided.
シールド用金属板を介在させて、クリップ形リードによ
り挾持し一体化したので、たとえ相互間に影響し合う回
路を混在させても、シールド用金属板によってその影響
を完全に防止することができた。Since the shielding metal plate was interposed and the circuits were sandwiched and integrated using clip-type leads, even if there were circuits that affected each other, the effects could be completely prevented by the shielding metal plate. .
又、シールド用金属板を介在して、二枚の回路基板を重
ね合せ、クリップ形リードにより挾持したので、高密度
化することができた。Furthermore, since two circuit boards were stacked on top of each other with a shielding metal plate interposed between them and held together by clip-shaped leads, it was possible to increase the density.
このように、混成回路相互間の影響防止と高密度化とを
同時に満足する混成ＩＣを得ることができ、産業上多大
な効果を奏する。In this way, it is possible to obtain a hybrid IC that satisfies both the prevention of influence between the hybrid circuits and the increase in density, which has great industrial effects.
第１図反型第７図は本発明の一実施例を示し、第１図は
デエアルインタイプの混成ＩＣの斜視図、第２図は第１
図の側面図、第３図はシールド用金属枚の斜視図、第４
図はシングルインタイブの混成ＩＣの斜視図、第５図は
第４図の側面図、第６図はシールド用金属枚の斜視図、
第７図はシールド用金属枚の他の実施例を示しその組立
要部の側面図である。
６．８．１４．１６．１７．１９・・・・・・・・・回
路基板、５．１３．２０・・・・・・・・・クリップ形
リード、＄１ ｌ
箪２圓
ｚ５固
Σワ回Figure 1 shows an example of the present invention; Figure 1 is a perspective view of a de-air-in type hybrid IC;
Figure 3 is a side view, Figure 3 is a perspective view of the metal sheet for shielding, Figure 4 is a perspective view of the metal sheet for shielding,
The figure is a perspective view of a single-in-type hybrid IC, Figure 5 is a side view of Figure 4, Figure 6 is a perspective view of a metal sheet for shielding,
FIG. 7 shows another embodiment of the shielding metal sheet and is a side view of the main parts of the assembly. 6.8.14.16.17.19...Circuit board, 5.13.20...Clip type lead, $1 l 箪2圓z5fixΣ Wa times
Claims (1)
の回路を形成していない面同志の間に介在し両基板間の
シールドを行なうためのシールド用金属板とから成り、
シールド用金属板を介在して２枚の回路基板を重ね合せ
、該重ね合せた２枚の回路基板を、クリップ形リード端
子により一体化して構成したことを特徴とする混成ＩＣ
。Consisting of two circuit boards with a circuit formed on one side, and a shielding metal plate interposed between the surfaces of the circuit boards on which no circuit is formed to provide shielding between the two boards,
A hybrid IC characterized in that two circuit boards are stacked with a shielding metal plate interposed therebetween, and the two stacked circuit boards are integrated with a clip-type lead terminal.
.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9547585A JPS61253899A (en) | 1985-05-07 | 1985-05-07 | Hybrid ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9547585A JPS61253899A (en) | 1985-05-07 | 1985-05-07 | Hybrid ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61253899A true JPS61253899A (en) | 1986-11-11 |
Family
ID=14138653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9547585A Pending JPS61253899A (en) | 1985-05-07 | 1985-05-07 | Hybrid ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61253899A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62101296U (en) * | 1985-12-17 | 1987-06-27 | ||
| JPH01176966U (en) * | 1988-06-02 | 1989-12-18 | ||
| JPH0513098U (en) * | 1991-07-26 | 1993-02-19 | 国際電気株式会社 | Circuit board |
-
1985
- 1985-05-07 JP JP9547585A patent/JPS61253899A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62101296U (en) * | 1985-12-17 | 1987-06-27 | ||
| JPH01176966U (en) * | 1988-06-02 | 1989-12-18 | ||
| JPH0513098U (en) * | 1991-07-26 | 1993-02-19 | 国際電気株式会社 | Circuit board |
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