JPS63263799A - Multilayer printed interconnection board - Google Patents
Multilayer printed interconnection boardInfo
- Publication number
- JPS63263799A JPS63263799A JP9924687A JP9924687A JPS63263799A JP S63263799 A JPS63263799 A JP S63263799A JP 9924687 A JP9924687 A JP 9924687A JP 9924687 A JP9924687 A JP 9924687A JP S63263799 A JPS63263799 A JP S63263799A
- Authority
- JP
- Japan
- Prior art keywords
- multilayer printed
- wiring circuit
- etching
- photoresist layer
- multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 238000007747 plating Methods 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電子装置の電気部品搭載用或いは裏面の相互配
線用として使用される多層印刷配線板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer printed wiring board used for mounting electrical components of electronic devices or for mutual wiring on the back side.
従来の多層印刷配線板は、銅張積層板に印刷・エッチン
グ等を行うことにより配線回路を形成した複数枚の印刷
配線板をプリプレグ等を接着層として積層したものであ
る。A conventional multilayer printed wiring board is one in which a plurality of printed wiring boards each having a wiring circuit formed thereon by printing, etching, etc. on a copper-clad laminate are laminated using prepreg or the like as an adhesive layer.
上述した従来の多層印刷配線板は複数枚の印刷配線板を
プリプレグ等を接着層として積層するため、積層する配
線板相互間に位置ずれが生じやすく、積層が非常に難し
いという欠点があった。The above-mentioned conventional multilayer printed wiring board has the drawback that since a plurality of printed wiring boards are laminated using prepreg or the like as an adhesive layer, misalignment easily occurs between the laminated wiring boards, making lamination extremely difficult.
本発明の目的は製造が容易な多層印刷配線板を提供する
ことにある。An object of the present invention is to provide a multilayer printed wiring board that is easy to manufacture.
本発明は銅張積層板に印刷・エッチング等を行うことに
よって所望の配線回路を形成し、該配線回路を絶縁性ホ
トレジスト層で保護し、該ホトレジスト層上に化学銅め
っき、電気銅めっき、エツチング等を行うことにより所
望の多層配線回路を形成したことを特徴とする多層印刷
配線板である。In the present invention, a desired wiring circuit is formed by printing, etching, etc. on a copper-clad laminate, the wiring circuit is protected with an insulating photoresist layer, and chemical copper plating, electrolytic copper plating, and etching are performed on the photoresist layer. This is a multilayer printed wiring board characterized in that a desired multilayer wiring circuit is formed by performing the above steps.
以下１本発明の一実施例を図により説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図（ａ）は、ガラスエポキシ基板１の両面に銅箔２
を張付けた銅張積層板３を示す。本発明は第１図（ａ）
に示すような銅張積層板３の両面に印刷・エッチング等
を行うことによって所望の配線回路４を形成しく第１図
（ｂ） ”） 、該配線回路４を絶縁性ホトレジスト層
５で保護しく第１図（ｃ） ） 、該ホトレジスト層５
上に化学銅めっき、電気銅めっき、エツチング等によっ
て所望の多層配線回路４′を形成することにより多層配
線板６を完成させたものである。FIG. 1(a) shows copper foil 2 on both sides of a glass epoxy substrate 1.
A copper-clad laminate 3 is shown. The present invention is shown in FIG. 1(a).
A desired wiring circuit 4 is formed by printing, etching, etc. on both sides of the copper-clad laminate 3 as shown in FIG. (FIG. 1(c)), the photoresist layer 5
A desired multilayer wiring circuit 4' is formed thereon by chemical copper plating, electrolytic copper plating, etching, etc., thereby completing the multilayer wiring board 6.
以上説明したように本発明は基板上に形成された配線回
路上にホトレジスト層を被覆し、その上にめっき、エツ
チング等により多層配線回路を形成するようにしたため
、上下の配線回路相互を接着剤にて積層する場合のよう
に接着剤が固まるまでの間に上下回路相互間に位置ずれ
を引き起こすことはなく、容易に製造できる効果を有す
るものである。As explained above, in the present invention, a photoresist layer is coated on a wiring circuit formed on a substrate, and a multilayer wiring circuit is formed on the photoresist layer by plating, etching, etc. Unlike in the case of lamination, there is no misalignment between the upper and lower circuits until the adhesive hardens, and this has the advantage of being easy to manufacture.
【図面の簡単な説明】
第１図（ａ）〜（ｄ）は本発明の一実施例を製造工程順
に示す断面図である。
１・・・ガラスエポキシ基板 ２・・・銅箔３・・・銅
張積層板 ４・・・配線回路４′・・・多層配
線回路 ５・・・ホトレジスト層６・・・多層印
刷配線板BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1(a) to 1(d) are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps. 1... Glass epoxy board 2... Copper foil 3... Copper-clad laminate board 4... Wiring circuit 4'... Multilayer wiring circuit 5... Photoresist layer 6... Multilayer printed wiring board
Claims (1)
って所望の配線回路を形成し、該配線回路を絶縁性ホト
レジスト層で保護し、該ホトレジスト層上に化学銅めっ
き、電気銅めっき、エッチング等を行うことにより所望
の多層配線回路を形成したことを特徴とする多層印刷配
線板。(1) Form a desired wiring circuit by printing, etching, etc. on a copper-clad laminate, protect the wiring circuit with an insulating photoresist layer, and perform chemical copper plating, electrolytic copper plating, and etching on the photoresist layer. A multilayer printed wiring board characterized in that a desired multilayer wiring circuit is formed by performing the above steps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9924687A JPS63263799A (en) | 1987-04-22 | 1987-04-22 | Multilayer printed interconnection board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9924687A JPS63263799A (en) | 1987-04-22 | 1987-04-22 | Multilayer printed interconnection board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63263799A true JPS63263799A (en) | 1988-10-31 |
Family
ID=14242342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9924687A Pending JPS63263799A (en) | 1987-04-22 | 1987-04-22 | Multilayer printed interconnection board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63263799A (en) |
-
1987
- 1987-04-22 JP JP9924687A patent/JPS63263799A/en active Pending
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