JPS63153894A - Multilayer printed interconnection board - Google Patents
Multilayer printed interconnection boardInfo
- Publication number
- JPS63153894A JPS63153894A JP29989786A JP29989786A JPS63153894A JP S63153894 A JPS63153894 A JP S63153894A JP 29989786 A JP29989786 A JP 29989786A JP 29989786 A JP29989786 A JP 29989786A JP S63153894 A JPS63153894 A JP S63153894A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- plating
- copper
- wiring
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 claims description 83
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 43
- 229910052802 copper Inorganic materials 0.000 claims description 43
- 239000010949 copper Substances 0.000 claims description 43
- 238000007747 plating Methods 0.000 claims description 29
- 238000007772 electroless plating Methods 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 238000000034 method Methods 0.000 description 7
- 239000003054 catalyst Substances 0.000 description 3
- 238000007788 roughening Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕 一
本発明は各種電子部品を搭載するのに用いられる多層プ
リント配線板に関し、特に基板の少くとも一面に層間絶
縁層を介して無電解メッキによる銅配線層を積み重ねた
構造のプリント配線板に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multilayer printed wiring board used for mounting various electronic components, and in particular electroless plating on at least one surface of the board via an interlayer insulating layer. This invention relates to a printed wiring board having a structure in which copper wiring layers are stacked.
従来の金属ベースプリント配線板は、主に基板の片面に
１層配線が形成されたものがある。この片面１層配線の
場合、部品の高密度搭載に限界があυ、どうしても２層
配線が必要な場合は、金属ベースの両面に絶縁層を介し
て銅箔を接着し、特殊なスルーホール工程によ〕両面の
配線層間のコンタクトをとって形成されていた。Conventional metal-based printed wiring boards mainly have one layer of wiring formed on one side of the board. In the case of this single-sided, single-layer wiring, there is a limit to high-density mounting of components, and if two-layer wiring is absolutely necessary, copper foil is bonded to both sides of the metal base via an insulating layer, and a special through-hole process is used. ] was formed by making contact between the wiring layers on both sides.
ところが、このスルーホール工程は複雑であり、そのた
め、金属ベース配線板の２層のものは高価であった。ま
た、スルーホールを形成するのに近年盛んになって来た
表面実装（ＳＭＴ）では、スルーホールのためそれだけ
余分の面積が必要となシ、実装密度が低下する欠点があ
った。However, this through-hole process is complicated, and therefore the two-layer metal-based wiring board is expensive. Furthermore, surface mounting (SMT), which has become popular in recent years for forming through holes, has the disadvantage that an extra area is required for the through holes, resulting in a reduction in packaging density.
本発明社上記のような欠点を除去するためになされたも
ので、その目的は、スルーホールを形成することなく、
無電解メッキによる銅配線層を積み重ねて形成すること
によ）、高密度の多層配線を容易に形成可能にした多層
プリント配線板を提供することにある。This invention was made in order to eliminate the above-mentioned drawbacks, and the purpose was to eliminate the need to form through holes.
An object of the present invention is to provide a multilayer printed wiring board in which high-density multilayer wiring can be easily formed by stacking copper wiring layers by electroless plating.
本発明に係る多層プリント配線板は、少くとも基板の一
方の面に形成された第１の銅配線層と、１該第１の銅配
線層上にそのコンタクト部分を開口させて被覆された１
間絶縁層と、該層間絶縁層の上に無電解メッキによりそ
のコンタクト部分を介して前記第１０銅配線層と導通接
続させて形成された配線パターンを有する下地Ｎ１メッ
キ層と、該下地Ｎ１メッキ層の表面にそれと同一パター
ンを有して形成された第２の銅配線層とを具備したもの
である。A multilayer printed wiring board according to the present invention includes a first copper wiring layer formed on at least one surface of a substrate, and a first copper wiring layer coated with a contact portion thereof opened on the first copper wiring layer.
an interlayer insulating layer, a base N1 plating layer having a wiring pattern formed on the interlayer insulating layer by electroless plating to be electrically connected to the tenth copper wiring layer through the contact portion thereof, and the base N1 plating layer. A second copper wiring layer is formed on the surface of the layer to have the same pattern as the first copper wiring layer.
したがって、本発明においては、基板の一方の面に形成
された第１の銅配線層上に層間絶縁層を介して無電解メ
ッキによシ下地Ｎｉメッキ層を形成したうえ、この下地
Ｎ１メッキ層の表面にそれと同一パターンの第２の銅配
線層を形成することによシ、スルーホールを用いること
なく、容易に多層配線を形成することができる。Therefore, in the present invention, a base Ni plating layer is formed by electroless plating on the first copper wiring layer formed on one side of the substrate via an interlayer insulating layer, and this base N1 plating layer is By forming a second copper wiring layer with the same pattern on the surface of the first copper wiring layer, multilayer wiring can be easily formed without using through holes.
以下、本発明を図面に示す実施例に基づいて詳細に説明
する。Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.
図面は本発明による多層プリント配線板の一実施例を示
す主要断面図であシ、ここではＡＡを金属ベースとして
用いた場合を示す。この実施例では、ますＡｔ金金属ペ
ース板上上、絶縁層２を介在させて接着された銅張多層
をエツチングによシバターニングして、第１の銅配線層
３を形成する。The drawing is a main cross-sectional view showing one embodiment of a multilayer printed wiring board according to the present invention, and here the case is shown in which AA is used as the metal base. In this embodiment, a first copper wiring layer 3 is formed by etching and patterning a copper clad multilayer bonded onto an At gold metal paste plate with an insulating layer 2 interposed therebetween.
次に、この銅配線層３の上に層間絶縁層４を被覆させて
形成したうえ、その絶縁層４上の第１の銅配線層３と接
続すべき部分を開口させてコンタクトホール５を形成す
る。次いで、前記層間絶縁層４上に無電解メッキにより
そのコンタクトホール５ｔ−介して所定の配線パターン
を有する下地Ｎ１メッキ層６を形成した後、この下地Ｎ
ｉ メッキ層６の上にそのパターンと同じ配線パターン
の第２の銅配線層７を無電解メッキで形成することにょ
シ、金属ベース板１０片面に形成された第１の銅配線層
３と第２の銅配線層７の間に該銅配線層７と同一の配線
パターンを有する下地Ｎ１ メッキ層６を中間メッキ配
線パターン層として形成するようにしたものである。Next, an interlayer insulating layer 4 is formed to cover this copper wiring layer 3, and a contact hole 5 is formed by opening a portion of the insulating layer 4 that is to be connected to the first copper wiring layer 3. do. Next, a base N1 plating layer 6 having a predetermined wiring pattern is formed on the interlayer insulating layer 4 through the contact hole 5t by electroless plating, and then the base N1 plated layer 6 is
i A second copper wiring layer 7 having the same wiring pattern as that pattern is formed on the plating layer 6 by electroless plating, and the first copper wiring layer 3 formed on one side of the metal base plate 10 and the second copper wiring layer 7 are formed on one side of the metal base plate 10. A base N1 plating layer 6 having the same wiring pattern as the copper wiring layer 7 is formed between the two copper wiring layers 7 as an intermediate plating wiring pattern layer.
ここで、下地Ｎｉ メッキ層６を形成するのは次の理由
による。すなわち、第１の銅配線層３つま９銅層３上に
眉間絶縁層４を介して無電解メッキによシ第２の銅層を
直接形成しようとすると、無電解銅メッキに必要なりロ
ム酸と硫酸混液による表面粗化工程とＰｄの塩酸溶液に
よる触媒附与工程で、これらの溶液はｐａ＝ｘ、ｏ程度
の強酸であるため、コンタクトホール５部分の第１の銅
層３が溶解してしまうことになる０それ故、本発明では
、第２の銅層を形成する前に、第１の銅層３に対する溶
解力が銅メッキの場合よりも小さい前処理工程（粗化工
程および触媒附与工程）を有する無電解Ｎｉ メッキに
よシ下地Ｎ１メッキ層６を中間メッキ配線パターン層と
して形成したうえ、その下地Ｎ１メツキ膚６の表面に無
電解鋼メッキによる第２の銅配線層７ｔ−形成して、第
２銅層形成工程におけるメッキ前処理を不要としたもの
である０
本発明者らの行った実験結果によると、第１表に示すよ
うに、Ｎｉ メッキの前処理工程での第４の銅層３の溶
解は銅メッキの場合の約半分であシ、第１の銅層３と下
地Ｎｉ メッキ層６との物理的・電気的接続が可能とな
った。Here, the reason why the base Ni plating layer 6 is formed is as follows. That is, if it is attempted to form the second copper layer directly on the first copper wiring layer 3 through the glabella insulating layer 4 by electroless plating, romic acid is required for electroless copper plating. During the surface roughening process using a mixed solution of Pd and sulfuric acid and the catalyst application process using a hydrochloric acid solution of Pd, the first copper layer 3 in the contact hole 5 portion is dissolved because these solutions are strong acids of the order of pa=x, o. Therefore, in the present invention, before forming the second copper layer, a pretreatment step (roughening step and catalyst A base N1 plating layer 6 is formed as an intermediate plating wiring pattern layer by electroless Ni plating, and a second copper wiring layer 7t is formed by electroless steel plating on the surface of the base N1 plating layer 6. According to the experimental results conducted by the present inventors, as shown in Table 1, in the Ni plating pretreatment process, the Ni plating pretreatment process is unnecessary. The melting of the fourth copper layer 3 was about half that of copper plating, and physical and electrical connection between the first copper layer 3 and the underlying Ni plating layer 6 became possible.
第１表
このとき、前記下地Ｎｉメッキ層６拡層間絶縁湘４を形
成後、表面粗化・触媒附与（粗化面８）とメツキレシス
ト層（第２銅層ネガパターン）９の形成を行った後、Ｎ
ｉを無電解メッキして形成した。また、この無電解メッ
キによる下地Ｎ１ メッキ層６の配線抵抗は比較的高
いので、その配線抵抗を低くするための第２の銅配線層
７が必要であるが、それは下地Ｎｉメッキ層６を形成し
た基板を銅メッキ液につけるだけで、非常に簡単に形成
できるのである。Table 1 At this time, after forming the base Ni plating layer 6 and the interlayer insulation layer 4, surface roughening/catalyst addition (roughened surface 8) and formation of a metal resist layer (second copper layer negative pattern) 9 were performed. After that, N
i was formed by electroless plating. Furthermore, since the wiring resistance of the base N1 plating layer 6 formed by this electroless plating is relatively high, a second copper wiring layer 7 is required to lower the wiring resistance, but it is necessary to form the base Ni plating layer 6. It can be formed very easily by simply dipping the plated board into a copper plating solution.
なお、上記実施例では金属ペース銅配線板の場合につい
て示したが、通常のガラスエポキシあるいは紙フェノー
ルを基板とした銅プリント配線板に適用しても同様の効
果が得られる。In the above embodiments, the case of a metal-based copper wiring board is shown, but the same effect can be obtained even if the invention is applied to a copper printed wiring board having a substrate made of ordinary glass epoxy or paper phenol.
また、上記実施例ではスルーホールを介さない片面多層
の場合であったが、スルーホール鋼メッキによる銅張両
面板を用いた通常のスルーホール基板のスルーホール部
での積層も、上記実施例と同様で可能である。In addition, although the above example was a case of single-sided multi-layering without through-holes, the above example also applies to lamination at the through-hole part of a normal through-hole board using a copper-clad double-sided board with through-hole steel plating. The same is possible.
また、上記実施例では２層配線の場合であったが、さら
に第３．第４の銅配線層を積み重ねた任意の多層配線を
形成することも可能である。In addition, although the above embodiment was a case of two-layer wiring, there is also a third layer wiring. It is also possible to form an arbitrary multilayer interconnection in which the fourth copper interconnection layer is stacked.
以上のように本発明によれば、基板の一方の面に形成さ
れた第１０銅配線層上に下地メッキ層を介して第２の銅
配線層を形成することによシ、無電解メッキ法での多層
配線が可能となシ、シかもその工程が簡易化されるので
、安価でかつ高密度多層配線のプリント配線板が得られ
る効果がある。As described above, according to the present invention, by forming the second copper wiring layer on the tenth copper wiring layer formed on one surface of the substrate via the base plating layer, electroless plating is performed. Since multi-layer wiring is possible and the process is simplified, it is possible to obtain a printed wiring board with high-density multi-layer wiring at low cost.
図面は本発明による多層プリント配線板の一実施例を示
す一部断面図である。
１・・・・金属ベース板、２・・・・絶縁層、３・・・
−第１の銅配線層、４・・・・層間絶縁層、５＠・・・
コンタクトホール、６・・Φ・下地メッキ層、Ｔφ・・
φ第２の銅配線層、８・・・・粗化面、９・・・・メツ
キレシスト膚。The drawing is a partially sectional view showing an embodiment of a multilayer printed wiring board according to the present invention. 1...Metal base plate, 2...Insulating layer, 3...
- first copper wiring layer, 4... interlayer insulating layer, 5@...
Contact hole, 6...Φ, base plating layer, Tφ...
φ second copper wiring layer, 8... roughened surface, 9... metsuki resist skin.
Claims (1)
、該第１の銅配線層上にそのコンタクト部分を開口させ
て被覆された層間絶縁層と、該層間絶縁層の上に無電解
メッキによりそのコンタクト部分を介して前記第１の銅
配線層と導通接続させて形成された配線パターンを有す
る下地Ｎｉメッキ層と、該下地Ｎｉメッキ層の表面にそ
れと同一パターンを有して形成された第２の銅配線層と
を具備することを特徴とする多層プリント配線板。a first copper wiring layer formed on at least one surface of the substrate; an interlayer insulating layer covering the first copper wiring layer with its contact portion opened; a base Ni plating layer having a wiring pattern formed by electroless plating to be electrically connected to the first copper wiring layer through the contact portion thereof; and a base Ni plating layer having the same pattern on the surface of the base Ni plating layer. A multilayer printed wiring board comprising a second copper wiring layer formed thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29989786A JPS63153894A (en) | 1986-12-18 | 1986-12-18 | Multilayer printed interconnection board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29989786A JPS63153894A (en) | 1986-12-18 | 1986-12-18 | Multilayer printed interconnection board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63153894A true JPS63153894A (en) | 1988-06-27 |
Family
ID=17878254
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29989786A Pending JPS63153894A (en) | 1986-12-18 | 1986-12-18 | Multilayer printed interconnection board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63153894A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008294459A (en) * | 2008-07-11 | 2008-12-04 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP2011071557A (en) * | 2011-01-07 | 2011-04-07 | Ibiden Co Ltd | Multilayer printed wiring board |
| US8006377B2 (en) | 1998-09-28 | 2011-08-30 | Ibiden Co., Ltd. | Method for producing a printed wiring board |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59115589A (en) * | 1982-12-22 | 1984-07-04 | 富士通株式会社 | Method of forming stereoscopic wiring |
-
1986
- 1986-12-18 JP JP29989786A patent/JPS63153894A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59115589A (en) * | 1982-12-22 | 1984-07-04 | 富士通株式会社 | Method of forming stereoscopic wiring |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8006377B2 (en) | 1998-09-28 | 2011-08-30 | Ibiden Co., Ltd. | Method for producing a printed wiring board |
| US8018045B2 (en) | 1998-09-28 | 2011-09-13 | Ibiden Co., Ltd. | Printed circuit board |
| US8020291B2 (en) | 1998-09-28 | 2011-09-20 | Ibiden Co., Ltd. | Method of manufacturing a printed wiring board |
| US8030577B2 (en) | 1998-09-28 | 2011-10-04 | Ibiden Co., Ltd. | Printed wiring board and method for producing the same |
| US8093507B2 (en) | 1998-09-28 | 2012-01-10 | Ibiden Co., Ltd. | Printed wiring board and method for producing the same |
| US8533943B2 (en) | 1998-09-28 | 2013-09-17 | Ibiden Co., Ltd. | Printed wiring board and method for producing the same |
| JP2008294459A (en) * | 2008-07-11 | 2008-12-04 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP2011071557A (en) * | 2011-01-07 | 2011-04-07 | Ibiden Co Ltd | Multilayer printed wiring board |
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