JPS63311731A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63311731A
JPS63311731A JP62147650A JP14765087A JPS63311731A JP S63311731 A JPS63311731 A JP S63311731A JP 62147650 A JP62147650 A JP 62147650A JP 14765087 A JP14765087 A JP 14765087A JP S63311731 A JPS63311731 A JP S63311731A
Authority
JP
Japan
Prior art keywords
bonding
films
wires
semiconductor device
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62147650A
Other languages
Japanese (ja)
Inventor
Shigeru Koshimaru
越丸　茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62147650A priority Critical patent/JPS63311731A/en
Publication of JPS63311731A publication Critical patent/JPS63311731A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To prevent the occurrence of the edge touch failure of bonding wires in bonding connection by a method wherein insulating films are formed on parts of a scribing line in such a way as to correspond to the bonding pad of each chip. CONSTITUTION:A scribing line 1 is a region where an Si substrate is bared and insulating films 2 are formed within the scribing line region 1. The places, where these films 2 are formed, are covered corresponding to a bonding pad 3 which is formed on each outer peripheral part of chip regions. Semiconductor devices separated into chips are mounted and fixed on an island 6 and thereafter, the pads 3 of the devices and bonding electrode parts (electrodes on the side of a lead frame) 5 of a lead frame are connected to each other by bonding through assembly bonding wires 4. At this time, as the films 2 are formed at places, where are within the region 1 left on the peripheries of the chips and correspond to the pads 3, the wires 4 are wired over the films 2 without fail. That is, the wires 4 are prevented from short-circuiting with the substrate 7 as there exist the films 2 and the edge touch failure of the wires can be made to nil.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特にダイシング用に形成さ
れるスクライブ線構造を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a scribe line structure formed for dicing.

〔従来の技術〕[Conventional technology]

従来、この踵の半導体装置は、ウェーハ状態からチップ
状態にするときダイヤモンドカッター等で個々のチップ
に分離するためのシリコン基板がむき出しになったスク
ライブ線を有している。このシリコン基板をむき出しに
しｔいるのは、ダイシングする際にスクライブ線上に酸
化膜や金属が形成されていると、切断線が乱れたり、あ
るいはカッターの歯が汚れたりするからである。Conventionally, this type of semiconductor device has a scribe line where the silicon substrate is exposed for separating into individual chips using a diamond cutter or the like when changing from a wafer state to a chip state. The reason why this silicon substrate is exposed is that if an oxide film or metal is formed on the scribe line during dicing, the cutting line will be disturbed or the cutter teeth will become dirty.

第４図はかかる従来の半導体装置の組立断面図である。FIG. 4 is an assembled sectional view of such a conventional semiconductor device.

第４図に示すようにこの半導体装置はシリコン基板１７
上にボンディングパッド１３が被着されており、まなこ
のパッド１３とスクライブ線１１を除く基板１７の表面
領域には表面保護膜１８が被覆されている。かかる半導
体装置をアイランド（島状領域）１６上に固着し、しか
る後パッド１３とリード側電極１５とをボンディングワ
イヤ１４によりボンディング接続している。これにより
シリコン基板１７上に形成された半導体素子（図示省略
）はリードに電気的に接続される。As shown in FIG. 4, this semiconductor device has a silicon substrate 17
A bonding pad 13 is adhered thereon, and the surface area of the substrate 17 except for the vertical pad 13 and the scribe line 11 is covered with a surface protective film 18 . Such a semiconductor device is fixed on an island (island-shaped region) 16, and then the pad 13 and the lead-side electrode 15 are bonded and connected by a bonding wire 14. Thereby, the semiconductor element (not shown) formed on the silicon substrate 17 is electrically connected to the leads.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体装置はシリコン基板がむき出しに
なったスクライブ２２　Ｍ　’Ａｉとなっているので、
ボンディング接続など半導体装置の組立の際にボンデイ
ングライヤ部分が、第４図に示すコーナ一部分す部のよ
うに、チップ分離用に形成されたスクライブ線に接触し
、いわゆるエツジタッチ不良を発生し易いという欠点が
ある。Since the conventional semiconductor device described above is a scribe 22 M'Ai with an exposed silicon substrate,
When assembling semiconductor devices, such as bonding connections, the bonding grinder comes into contact with the scribe line formed for chip separation, as shown in the corner part shown in Figure 4, which tends to cause so-called edge-touch defects. There is.

本発明の目的は、かかるボンディング接続におけるボン
ディング線のエツジタッチ不良を解消するような半導体
装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that eliminates edge touch defects of bonding lines in such bonding connections.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置は、チップ分離用に設けられたスク
ライブ線上の一部に各チップのボンディングパッドに対
応して絶縁、膜を形成するように構成される。The semiconductor device of the present invention is configured such that insulation and films are formed on a portion of the scribe line provided for chip separation in correspondence with the bonding pads of each chip.

〔実施例〕〔Example〕

次に、本発明の一実施例について図面を参照して説明す
る。Next, an embodiment of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例を説明するための半導体装Ｂ
ｉｔの平面図である。この半導体装置はチップに分■す
る萌の状態を示している。FIG. 1 shows a semiconductor device B for explaining one embodiment of the present invention.
FIG. This semiconductor device is in a state of being separated into chips.

第１図に示すように、スクライブ線１はシリコン基板が
むき出しになった領域であり、そのスクライブ線領域１
内に絶縁膜２が形成されている。As shown in FIG. 1, the scribe line 1 is an exposed area of the silicon substrate;
An insulating film 2 is formed inside.

この絶縁膜２を形成する個所にはチップ領域の各外周部
に形成されるボンディング用パッド３に対応して被覆さ
れる。The portions where this insulating film 2 is to be formed are coated in correspondence with the bonding pads 3 formed on each outer periphery of the chip area.

第２図は本発明の半導体装置を組立した際の平面図であ
る。FIG. 2 is a plan view of the assembled semiconductor device of the present invention.

第２図に示すように、各チップに分離された半導体装置
をアイランド（島状領域）６上にマウント固着し、しか
る後、半導体装置のパラ１〈３とリードフレームのボン
ディング電極部５とを組立ボンディングワイヤ４により
ボンディング接続した状態である。このときチップの周
囲に残っているスクライブ線領域１内のパッド３の対応
個所には絶縁膜２が形成されているのでポンティングワ
イヤ４は必ず絶縁膜２の上方に配線される。As shown in FIG. 2, the semiconductor device separated into each chip is mounted and fixed on an island (island-like area) 6, and then the semiconductor device 1<3 and the bonding electrode part 5 of the lead frame are connected. This is a state in which the bonding connection is made using the assembled bonding wire 4. At this time, since the insulating film 2 is formed at a location corresponding to the pad 3 in the scribe line region 1 remaining around the chip, the ponting wire 4 is always wired above the insulating film 2.

第３図は」二連した第２図におけるＡ−Ａ’線の縦断面
図である。FIG. 3 is a longitudinal sectional view taken along line AA' in FIG. 2.

第３図に示すようにシリコン基板上上にボンディングパ
ッド３と絶縁膜２および表面保護膜８を形成された半導
体装置がアイランドＧ上にマウン１−　’され、ボンデ
ィングワイヤ１１によりパッド３とリード側電極５とを
接続している。かがる半導体装置において、ボンデイン
クワイヤ４は絶縁膜２があるのでシリコン基板７とショ
ー）・することはない。As shown in FIG. 3, a semiconductor device in which a bonding pad 3, an insulating film 2, and a surface protection film 8 are formed on a silicon substrate is mounted on an island G, and bonding wires 11 are used to connect the pad 3 and the lead side. It is connected to the electrode 5. In the semiconductor device to be bonded, the bonding wire 4 does not come into contact with the silicon substrate 7 because of the insulating film 2.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は複数個の半導体′ｉＡ置
を形成したウェーハ上のスクライブ線の一部に絶縁成金
形成することにより、ボンディング接続などの半導体装
置の組立時におけるワイヤのエツジタッチ不良を皆無に
することができる効果がある。As explained above, the present invention prevents edge touch defects of wires during assembly of semiconductor devices such as bonding connections by forming an insulating layer on a part of the scribe line on a wafer on which a plurality of semiconductor layers are formed. There are effects that can be completely eliminated.

図面の簡りｉな説明 第１図は本発明の一実施例を説明するための半導体装置
の平面図、第２図は本発明による半導体装１１′げにボ
ンディング接続を行った状態のＪ１面図、第３図は第２
Ｕ′Ａに示す、ｌ−Ａ′線線断断面図第４図は従来の一
例を説明するための半導体装置の組立断面図である。Brief Description of the Drawings FIG. 1 is a plan view of a semiconductor device for explaining an embodiment of the present invention, and FIG. 2 is a J1 side view of a state in which bonding connections are made to a semiconductor device 11' according to the present invention. , Figure 3 is the second
FIG. 4, which is a sectional view taken along the line 1-A' shown at U'A, is an assembled sectional view of a semiconductor device for explaining a conventional example.

１゛・・・スクライブ線領域、２・・・絶縁膜、３・・
ポンディグパッド、４・・・ボンデインクワイヤ、５　
・リード側電極、６・・・アイランド、７・・・シリコ
ン１占板、８・・・ｋ面保護膜。1゛...Scribe line area, 2...Insulating film, 3...
Bonding pad, 4... Bonding wire, 5
・Lead side electrode, 6...Island, 7...Silicon 1 board, 8...K-plane protective film.

代理人　升埋士　内　原　　昔　゛ （・Agent Masu Burialist Uchihara Long ago (・

Claims (1)

【特許請求の範囲】[Claims] シリコン基板上に半導体素子を形成した半導体装置にお
いて、チップ分離用に設けられた境界線上の一部に各チ
ップのボンディングパッドに対応して絶縁膜を形成した
ことを特徴とする半導体装置。1. A semiconductor device in which semiconductor elements are formed on a silicon substrate, characterized in that an insulating film is formed on a part of a boundary line provided for chip separation in correspondence with bonding pads of each chip.
JP62147650A 1987-06-12 1987-06-12 Semiconductor device Pending JPS63311731A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62147650A JPS63311731A (en) 1987-06-12 1987-06-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62147650A JPS63311731A (en) 1987-06-12 1987-06-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63311731A true JPS63311731A (en) 1988-12-20

Family

ID=15435147

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62147650A Pending JPS63311731A (en) 1987-06-12 1987-06-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63311731A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100512395B1 (en) * 2000-07-31 2005-09-07 엔이씨 일렉트로닉스 가부시키가이샤 Semiconductor wafer, semiconductor device and manufacturing method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100512395B1 (en) * 2000-07-31 2005-09-07 엔이씨 일렉트로닉스 가부시키가이샤 Semiconductor wafer, semiconductor device and manufacturing method therefor

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