JPS63311751A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63311751A JPS63311751A JP14764387A JP14764387A JPS63311751A JP S63311751 A JPS63311751 A JP S63311751A JP 14764387 A JP14764387 A JP 14764387A JP 14764387 A JP14764387 A JP 14764387A JP S63311751 A JPS63311751 A JP S63311751A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- resistor
- oxide film
- contact hole
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 230000001681 protective effect Effects 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000002161 passivation Methods 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 2
- 235000006732 Torreya nucifera Nutrition 0.000 description 1
- 244000111306 Torreya nucifera Species 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に於て特にボンディングバンドの構
造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates particularly to the structure of a bonding band in a semiconductor device.
第３図１３）は従来の半導体装置のボンディングパッド
近傍の平面図、同図（ｂ）は同図（ａ）のＡ−Ａ断面図
である。第３図において、基板１１の上の絶縁酸化膜２
の上に設けられたボンディングパッド１４と保護抵抗１
３の一端部とはボンディングパッド１４から一旦引出さ
れた配線１７、及びコンタクトホール１５を通して接続
されている。また、保護抵抗１３の他端はコンタクトホ
ール１６を通して配線１８に導電接続されている。FIG. 3(b) is a plan view of the vicinity of a bonding pad of a conventional semiconductor device, and FIG. 3(b) is a sectional view taken along the line AA in FIG. 3(a). In FIG. 3, an insulating oxide film 2 on a substrate 11 is shown.
The bonding pad 14 and the protective resistor 1 provided on the
3 through a wiring 17 drawn out from the bonding pad 14 and a contact hole 15. Further, the other end of the protective resistor 13 is conductively connected to a wiring 18 through a contact hole 16.
上述した従来の半導体装置は、入出力素子の保護抵抗が
一旦アルミニウム等の配線を通してボンディングパッド
部へつながっている為、保護抵抗の値によってはそれが
チップ上で占める面積は比較的大きなものとなり、チッ
プサイズを小さくしようとする場合の妨げとなる。In the conventional semiconductor device described above, the protective resistor of the input/output element is connected to the bonding pad section through wiring made of aluminum or the like, so depending on the value of the protective resistor, the area occupied by the protective resistor on the chip becomes relatively large. This becomes an obstacle when trying to reduce the chip size.
本発明は上述した問題点を解決する為に、保護抵抗の上
に絶縁膜をはさんでボンディングパッドを重ね、前記絶
縁膜にあけられたコンタクトホールを通して前記保護抵
抗とボンディングパッドとを接続している。In order to solve the above-mentioned problems, the present invention stacks a bonding pad on a protective resistor with an insulating film sandwiched therebetween, and connects the protective resistor and the bonding pad through a contact hole made in the insulating film. There is.
つぎに本発明を実施例によシ説明する。 Next, the present invention will be explained using examples.
第１図（ａｌは本発明の一実施例のボンディングパッド
近傍の平面図、同図（ｂｌは同図［ａｌのＡ−Ａ断面図
である。第１図（ａｌ 、 （ｂ）において、基板１を
被う絶縁酸化膜２の上にポリシリコンの保護抵抗３が形
成され、さらにこの抵抗３の上部には酸化膜２′を介し
てボンディングパッド４が形成され、保護抵抗３の一端
部とボンディングパッド４とは、間に介在する絶縁酸化
膜２′にあけられたコンタクトホール５を通して導電接
続され、捷た、抵抗３の他端部は、その上の酸化膜２′
にあけられたコンタクトホール６を通して、引出し配線
７の一端に導電接続されている。なお、ボンディングパ
ッド４の中央部だけは外部に露出され、配線その他はパ
ラ／べ・−ジョン膜８により被われ保護されている。FIG. 1 (al is a plan view of the vicinity of the bonding pad of an embodiment of the present invention, FIG. A polysilicon protective resistor 3 is formed on an insulating oxide film 2 covering the resistor 1, and a bonding pad 4 is formed on the resistor 3 with an oxide film 2' interposed therebetween. The bonding pad 4 is conductively connected to the bonding pad 4 through a contact hole 5 formed in the insulating oxide film 2' interposed therebetween, and the other end of the resistor 3, which is cut off, is connected to the oxide film 2' thereon.
It is conductively connected to one end of a lead wiring 7 through a contact hole 6 formed in the . Note that only the central portion of the bonding pad 4 is exposed to the outside, and the wiring and other parts are covered and protected by a para/vehicle film 8.
第２図（ａ）は本発明の他の実施例のボンディングパッ
ド近傍の平面図、同図ｔｂ）は同図（ａ）のＡ−Ａ断面
図である。第２図（ａ） 、 （ｂ）において、本例の
保護抵抗１３は、基板１に不純物の拡散により形成され
た拡散抵抗であり、拡散抵抗１３を含む基板面が絶縁酸
化膜２で被われ、酸化膜２にあけられたコンタクトホー
ル５を通して拡散抵抗１３の上に設けたボンディングパ
ッド４と拡散抵抗１３の一端部が導電接続され、拡散抵
抗１３の他端と引出し配線７との間は、コンタクトホー
ル６を通して接続されている。また、ボンディングパッ
ドの表面を除いてその他はパッシベーション膜８で保護
されているのは第１図の例と同様である。FIG. 2(a) is a plan view of the vicinity of a bonding pad according to another embodiment of the present invention, and FIG. 2(tb) is a sectional view taken along the line AA in FIG. 2(a). In FIGS. 2(a) and 2(b), the protective resistor 13 of this example is a diffused resistor formed by diffusion of impurities into the substrate 1, and the substrate surface including the diffused resistor 13 is covered with an insulating oxide film 2. The bonding pad 4 provided on the diffused resistor 13 and one end of the diffused resistor 13 are electrically connected through the contact hole 5 made in the oxide film 2, and the connection between the other end of the diffused resistor 13 and the lead wire 7 is as follows. They are connected through contact holes 6. Further, except for the surface of the bonding pad, the rest is protected by a passivation film 8, as in the example shown in FIG.
以上説明したように本発明は、保護抵抗とボンディング
パッドとを絶縁膜を間にはさんで重ねて形成し、絶縁膜
にあけたコンタクトホールな通して保護抵抗をボンディ
ングパッドに接続することにより、従来保護抵抗のため
にとられていたチップ上の面ｆ＊を削減することができ
る。As explained above, in the present invention, a protective resistor and a bonding pad are stacked with an insulating film sandwiched between them, and the protective resistor is connected to the bonding pad through a contact hole formed in the insulating film. The surface f* on the chip, which was conventionally reserved for the protection resistor, can be reduced.
第１図ｔａｌは本発明の一実施例のボンディングパッド
近傍の平面図、同図（ｂｌは同図Ｔａ）のＡ−Ａ断面図
、第２図（ａｌは本発明の他の実施例のボンディングパ
ッド近傍の平面図、同図（ｂｌは同図ｔａ）のＡ−Ａ断
面図、第３図（ａ）は従来の半導体装置のボンディング
パッド近傍の平面図、同図（ｂｌは同図（ａｌのＡ−Ａ
断面図である。
１・・・・・・基板、２，２′・・・・・・絶縁酸化膜
、３，１３・・・・・・保護抵抗、４・・・・・・ボン
ディングパッド、５，６・・・・・・コンタクトホール
、７・・・・・・引出し配線、８・・・・・・パッシベ
ーション膜。
代理人 弁理士 内 原 音
＄１１Ｊ
茅 ２ 凹FIG. 1 (tal) is a plan view of the vicinity of the bonding pad of one embodiment of the present invention, a sectional view taken along the line A-A in the same figure (bl is Ta in the same figure), and FIG. 3(a) is a plan view of the vicinity of the bonding pad of a conventional semiconductor device; FIG. 3(a) is a plan view of the vicinity of the bonding pad of a conventional semiconductor device; A-A of
FIG. 1... Substrate, 2, 2'... Insulating oxide film, 3, 13... Protective resistor, 4... Bonding pad, 5, 6... . . . Contact hole, 7 . . . Output wiring, 8 . . . Passivation film. Agent Patent Attorney Oto Uchihara $11J Kaya 2 concave
Claims (1)
れた入力または出力用保護抵抗とが同一基板上に形成さ
れている半導体装置において、前記ボンディングパッド
は絶縁膜を間に介在させて前記保護抵抗の上に形成され
、かつ、前記絶縁膜にあけられたコンタクトホールを通
して直下の前記保護抵抗と導電接続されていることを特
徴とする半導体装置。In a semiconductor device in which a bonding pad and an input or output protection resistor connected to the bonding pad are formed on the same substrate, the bonding pad is formed on the protection resistor with an insulating film interposed therebetween. , and is electrically conductively connected to the protective resistor directly below through a contact hole formed in the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14764387A JPS63311751A (en) | 1987-06-12 | 1987-06-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14764387A JPS63311751A (en) | 1987-06-12 | 1987-06-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63311751A true JPS63311751A (en) | 1988-12-20 |
Family
ID=15434978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14764387A Pending JPS63311751A (en) | 1987-06-12 | 1987-06-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63311751A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06151424A (en) * | 1992-02-19 | 1994-05-31 | Nec Corp | Semiconductor device |
-
1987
- 1987-06-12 JP JP14764387A patent/JPS63311751A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06151424A (en) * | 1992-02-19 | 1994-05-31 | Nec Corp | Semiconductor device |
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