JPS6329949U - - Google Patents
Info
- Publication number
- JPS6329949U JPS6329949U JP12169486U JP12169486U JPS6329949U JP S6329949 U JPS6329949 U JP S6329949U JP 12169486 U JP12169486 U JP 12169486U JP 12169486 U JP12169486 U JP 12169486U JP S6329949 U JPS6329949 U JP S6329949U
- Authority
- JP
- Japan
- Prior art keywords
- recess
- ceramic
- height
- semiconductor chip
- ceramic frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の一実施例を示す図、第２図は
セラミツクフレームの高さと特性インピーダンス
のずれとの関係を例示する図、第３図は従来の高
速集積回路用パツケージの構成例を示す図である
。
１……セラミツクフレーム、２……セラミツク
基板、３―１，３―２，３―３，３―１′，３―
２′，３―３′……信号線、４……接地電極、４
―１，４―１′……接地電極メタライズ層、５…
…メタライズ層、６……キヤビテイ、７―１，７
―２，７―３，７―１′，７―２′，７―３′…
…信号線リード、８，８′……アース線リード。
Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram illustrating the relationship between the height of the ceramic frame and the deviation in characteristic impedance, and Fig. 3 is a diagram showing an example of the configuration of a conventional package for high-speed integrated circuits. FIG. 1... Ceramic frame, 2... Ceramic substrate, 3- 1 , 3- 2 , 3- 3 , 3- 1 ', 3-
2 ', 3- 3 '... Signal line, 4... Ground electrode, 4
- 1 , 4 - 1 '...Ground electrode metallized layer, 5...
...metalized layer, 6...cavity, 7- 1 ,7
- 2,7- 3,7- 1 ',7- 2 ',7- 3 '...
...Signal line lead, 8,8'...Earth line lead.
Claims (1)
に半導体チツプを収容するとともに、該基板の凹
部のある側の凹部以外の部分に信号線路を設けて
半導体チツプを接続し、セラミツク基板上に該半
導体チツプを囲んでセラミツクフレームを設け、
該セラミツクフレーム上部を気密封止する集積回
路用パツケージにおいて、 前記セラミツク基板上に接地電極を設けて前記
信号線路を該接地電極の部分にコプレーナ線路と
して形成し、前記セラミツクフレームの上面にメ
タライズ層を設けて該セラミツクフレームの側面
を介して接地電極に接続するとともに該メタライ
ズ層に導電性を有する蓋を施して封止し、該セラ
ミツクフレームの高さを使用周波数において前記
コプレーナ線路の特性インピーダンスに影響を及
ぼさない高さに選定したことを特徴とする高速集
積回路用パツケージ。[Claim for Utility Model Registration] A semiconductor chip is accommodated in the recess of a ceramic substrate having a recess in the center, and a signal line is provided in a portion of the substrate other than the recess on the side where the recess is located to connect the semiconductor chip. , providing a ceramic frame surrounding the semiconductor chip on a ceramic substrate;
In the integrated circuit package in which the upper part of the ceramic frame is hermetically sealed, a ground electrode is provided on the ceramic substrate, the signal line is formed as a coplanar line in the part of the ground electrode, and a metallized layer is formed on the upper surface of the ceramic frame. The metallized layer is sealed with a conductive lid, and the height of the ceramic frame is set to influence the characteristic impedance of the coplanar line at the operating frequency. A package for high-speed integrated circuits characterized by having a height that does not affect the height of the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12169486U JPS6329949U (en) | 1986-08-08 | 1986-08-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12169486U JPS6329949U (en) | 1986-08-08 | 1986-08-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6329949U true JPS6329949U (en) | 1988-02-27 |
Family
ID=31011202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12169486U Pending JPS6329949U (en) | 1986-08-08 | 1986-08-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6329949U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0269967A (en) * | 1988-09-05 | 1990-03-08 | Nippon Telegr & Teleph Corp <Ntt> | Package for high speed/high frequency integrated circuit |
| JPH0372658A (en) * | 1989-08-11 | 1991-03-27 | Fujitsu Ltd | Package for electronic parts |
| JPH0624239U (en) * | 1992-08-11 | 1994-03-29 | 天竜丸澤株式会社 | Electromagnetic spring clutch |
-
1986
- 1986-08-08 JP JP12169486U patent/JPS6329949U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0269967A (en) * | 1988-09-05 | 1990-03-08 | Nippon Telegr & Teleph Corp <Ntt> | Package for high speed/high frequency integrated circuit |
| JPH0372658A (en) * | 1989-08-11 | 1991-03-27 | Fujitsu Ltd | Package for electronic parts |
| JPH0624239U (en) * | 1992-08-11 | 1994-03-29 | 天竜丸澤株式会社 | Electromagnetic spring clutch |
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