JPS6329357B2 - - Google Patents
Info
- Publication number
- JPS6329357B2 JPS6329357B2 JP58093123A JP9312383A JPS6329357B2 JP S6329357 B2 JPS6329357 B2 JP S6329357B2 JP 58093123 A JP58093123 A JP 58093123A JP 9312383 A JP9312383 A JP 9312383A JP S6329357 B2 JPS6329357 B2 JP S6329357B2
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- signal
- shift register
- speed
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Memory System (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58093123A JPS59223987A (ja) | 1983-05-26 | 1983-05-26 | デジタル信号記憶装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58093123A JPS59223987A (ja) | 1983-05-26 | 1983-05-26 | デジタル信号記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59223987A JPS59223987A (ja) | 1984-12-15 |
| JPS6329357B2 true JPS6329357B2 (cs) | 1988-06-13 |
Family
ID=14073741
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58093123A Granted JPS59223987A (ja) | 1983-05-26 | 1983-05-26 | デジタル信号記憶装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59223987A (cs) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999000734A1 (fr) * | 1997-06-27 | 1999-01-07 | Hitachi, Ltd. | Module memoire et systeme de traitement de donnees |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52124827A (en) * | 1976-04-13 | 1977-10-20 | Nec Corp | Semiconductor memory unit |
| JPS5893123A (ja) * | 1982-11-11 | 1983-06-02 | シャープ株式会社 | 押釦スイツチ |
-
1983
- 1983-05-26 JP JP58093123A patent/JPS59223987A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999000734A1 (fr) * | 1997-06-27 | 1999-01-07 | Hitachi, Ltd. | Module memoire et systeme de traitement de donnees |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59223987A (ja) | 1984-12-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3979716B2 (ja) | クロック同期型メモリ装置及びそのスケジューラ回路 | |
| KR100316813B1 (ko) | 상이한 타이밍 신호들을 조정하는 반도체 장치 | |
| JP4315552B2 (ja) | 半導体集積回路装置 | |
| US6381684B1 (en) | Quad data rate RAM | |
| JP4477425B2 (ja) | レイテンシ回路を備える半導体メモリ装置及びそのデータ出力制御方法 | |
| US7633326B2 (en) | Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof | |
| EP0218830A2 (en) | A memory test apparatus | |
| JPH0480350B2 (cs) | ||
| US5033001A (en) | Dual mode memory read cycle time reduction system which generates read data clock signals from shifted and synchronized trigger signals | |
| US20080091869A1 (en) | High speed, low current consumption fifo circuit | |
| US5416746A (en) | Memory circuit for alternately accessing data within a period of address data | |
| JP3270831B2 (ja) | 半導体装置 | |
| KR0154741B1 (ko) | 듀얼포트 메모리 장치 및 듀얼포트 메모리 장치의 시리얼데이타 출력방법 | |
| US6252527B1 (en) | Interface unit for serial-to-parallel conversion and/or parallel-to-serial conversion | |
| JPS6329357B2 (cs) | ||
| WO1996021278A1 (en) | Interleaved and sequential counter | |
| US20040217795A1 (en) | Delay adjusting apparatus providing different delay times by producing a plurality of delay control signals | |
| JP2007200555A (ja) | クロック同期型メモリ装置及びそのスケジューラ回路 | |
| JPS59191657A (ja) | デジタル・パタ−ン発生器 | |
| JP2788729B2 (ja) | 制御信号発生回路 | |
| JPH06124586A (ja) | 半導体記憶装置 | |
| JPH0225567B2 (cs) | ||
| JPS63136814A (ja) | デイジタル遅延回路 | |
| JP3003328B2 (ja) | クロック信号回路 | |
| JPH0240192A (ja) | シリアルアクセス動作の可能な半導体記憶装置 |