JPS6329357B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal storage device that uses low-speed memory to store high-speed digital signals.

BACKGROUND OF THE INVENTION Measuring instruments such as logic analyzers and transient digitizers require high speed mass storage. Memory elements include memory such as random access memory (RAM) and shift memory.
Although there are registers, high-speed memory elements are generally expensive, making it difficult to increase their capacity. On the other hand, since low-speed memory elements are inexpensive, it is easy to increase their capacity.
Therefore, it has been proposed in Japanese Patent Publication No. 43543/1983 to obtain an inexpensive high-speed large-capacity storage device by combining a high-speed small-capacity storage element and a low-speed large-capacity storage element.
This uses a serial input parallel output type shift register as a high speed small capacity storage element and a RAM as a low speed large capacity storage element, and stores digital input signals as follows. That is, a digital input signal is serially input into a shift register, and after storing the input signal in all bits, each bit is output in parallel and latched into a latch circuit, and the output of the latch circuit is
Stored in RAM. Therefore, if the shift register is M (an integer greater than or equal to 2) bits, then the RAM
The write speed required for the shift register may be 1/M of the write speed of the shift register. but,
Since a latch circuit is connected between the shift register and RAM, the write speed actually required for RAM must take into account the write speed and read speed of the latch circuit. It had to be faster than 1/M of the speed. Furthermore, the writing speed of the latch circuit had to be very high in order to avoid missing even a portion of the input signal when storing the input signal.

OBJECTS OF THE INVENTION Therefore, one of the objects of the present invention is to
An object of the present invention is to provide a high-speed, large-capacity digital signal storage device that combines a register and a memory.

Another object of the present invention is to provide a digital signal storage device that does not require connection of a storage element such as a latch circuit between a shift register and a memory.

Summary of the Invention The digital signal storage device of the present invention uses N (N is an integer of 3 or more) series-input serial-output type shift registers as high-speed small-capacity storage elements, and a memory such as RAM as a low-speed large-capacity storage element. is used. If a digital input signal is commonly supplied to N shift registers, each shift register receives a digital input signal by a first clock signal such that the second shift register starts writing after the first shift register completes writing. The signals are sequentially stored for a predetermined number of clocks. After each shift register completes writing, it sequentially outputs the stored digital signals to the corresponding memory using a second clock signal having a lower frequency than the first clock signal. That is, out of N shift registers, only 1 is in write operation.
The other shift registers are in read operation. Since N is an integer greater than or equal to 3, the read speed of each shift register may be 1/(N-1) of the write speed, and the write speed of the memory may also be that slow. Furthermore, since the output of the shift register is supplied to the memory without passing through a storage element such as a latch circuit, the low read speed obtained by the combination of shift registers can be directly used as the write speed of the memory. Therefore, compared to the prior art described above, an efficient high-speed, large-capacity digital signal storage device can be obtained.

Embodiment of the Invention Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of a preferred embodiment of the present invention. The digital input signal from the input terminal 10 is transferred to four (N=4) series input serial output type shift registers (S/R) 12-1~
Supplied to the input terminal of 12-4. Each of these shift registers 12-1 to 12-4 has, for example, 3 bits, but the number of bits is preferably an integral multiple of (N-1). Shift register 12-1 to 12
A first clock signal φ1 for writing or a second clock signal φ1 for reading having a lower frequency (for example, 1/3) than the first clock signal φ1 is connected to each clock terminal of each clock signal φ1.
A clock signal φ2 is supplied via multiplexers (MUX) 14-1 to 14-4, which are selection means. The serial output digital signals of the shift registers 12-1 to 12-4 are each sent to a level converter 16-1.
~16-4 via the corresponding memory (e.g.
RAM) 18-1 to 18-4. The level converters 16-1 to 16-4 are connected to the logic system (for example, ECL) of the shift registers 12-1 to 12-4.
When the logic system (for example, TTL system) of the memories 18-1 to 18-4 is different from that of the memories 18-1 to 18-4, the voltage level of the output signal of the shift register is converted to the voltage level of the input signal of the memory. Therefore, if the shift register and memory have the same logic system, the level converters 16-1 to 16-4 are unnecessary.

The clock generating means 20 comprises a reference clock generator 22, such as a crystal oscillator, and a frequency divider 24 which divides the frequency of the output clock signal of the clock generator 22 (for example, divides the frequency by one-third). The outputs of the clock generator 22 and frequency divider 24 are a first clock signal .phi.1 and a second clock signal .phi.2, respectively, and are supplied to multiplexers 14-1 to 14-4. The control means 26 includes a 2-bit counter 28 that counts the second clock signal φ2 from the frequency divider 24, and a decoder 30 that generates four control signals C1 to C4 in accordance with the 2-bit output of the counter 28. do. The "low" and "high" level periods of the control signals C1 to C4 correspond to 3 bits and 12 bits of the first clock signal φ1, respectively, and this clock signal φ1 is a 4-phase signal with 16 bits and one cycle. . The timing relationship of these signals φ1 and φ2 and C1 to C4 is shown in FIG.

The control signals C1 to C4 are each sent to a multiplexer 14.
-1 to 14-4, the first clock signal φ1 is selected when the control signal is at the "low" level, and the second clock signal φ is selected when the control signal is at the "high" level.
Make sure to select 2. In addition, control signals C1 to C
4 is memory 18-1~ at its "high" level.
18-4 in write mode, and gate 32-
1 to 32-4 are opened to supply the second clock signal φ2 to the clock ends of address counters 34-1 to 34-4. Therefore, counters 34-1 to 34
-4 supplies an address signal that sequentially increases (or decreases) while the memories 18-1 to 18-4 are in the write mode to the address ends of the memories 18-1 to 18-4.

Next, the operation of the digital signal generator shown in Fig. 1 is as follows.
This will be explained with reference to the timing diagram of FIG. For example, at time T1, if the control signal C1 is at the "low" level and the other control signals C2-C3 are at the "high" level, the multiplexer 14-1 selects the first clock signal φ1 and the other control signals C2-C3 are at the "high" level. The multiplexers 14-2 to 14-4 receive the second clock signal φ2.
Select. Further, the gate 32-1 is closed, and the other gates 32-2 to 32-4 are opened. Shift
The register 12-1 inputs the digital input signal while sequentially shifting it by three bits of the first clock signal φ1 in synchronization with the first clock signal φ1. At time T2, the second control signal C2 is at a "low" level, and the other control signals C1, C3, and C4 are at a "high" level. Shift register 1
2-2 stores the next digital input signal while shifting it by 3 bits of the first clock signal φ1. On the other hand, shift register 12-1 is a low-speed second
It is shifted by the clock signal φ2 and outputted from the first input digital input signal to the memory 18-1 in write mode (via a level converter if necessary). Also, at this time, gate 32-1
Since the counter 34-1 is open, the counter 34-1 counts the second clock signal φ2 and sends the address signal to the memory 1.
Supply to 8-1.

Similarly, between time points T3 and T4, shift register 12-3 performs a shifting operation of the digital input signal by the first clock signal φ1, and memory 18-3 is not in write mode and gate 3
2-3 are closed. On the other hand, shift register 1
2-1, 12-2 and 12-4 transfer the stored digital input signals to the corresponding memories 18-1, 18-2 and 18-4 in response to the second clock signal φ2. Furthermore, at times T4 and T5, the shift register 12-4 shifts the digital input signal using the first clock signal φ1, and the other shift registers 12-1 to 12-3 shift the stored digital signal using the second clock signal φ1. The input signals are transferred to memories 18-1 to 18-3, respectively. Therefore, the shift register 12-1 is stored at times T1 and T.
The digital input signal stored between two times is transferred to the memory 18-1 between times T2 and T5, and a new digital input signal is stored between times T5 and T6 in response to the first clock signal. The same goes for the other shift registers, and the above-described operation is repeated thereafter. Therefore, the writing speed of the memories 18-1 to 18-4 may be one third of the writing speed of the shift registers 12-1 to 12-4, so that inexpensive low-speed large-capacity memories can be used.

Note that when the shift registers 12-1 to 12-4 output the stored digital input signals to the memories 18-1 to 18-4 in synchronization with the second clock signal φ2, the digital input signals from the input terminal 10 are simultaneously output. It takes in. The digital input signal taken in in synchronization with the second clock signal φ2 is output in synchronization with the first clock signal φ1, but during this output period, the memory is not in write mode and the gate is closed. The digital input signal stored in the shift register by the second clock signal is not transferred to memory. After the storage of the digital input signal is completed, in order to read the contents of the memories 18-1 to 18-4, it is sufficient to read these memories sequentially three bits at a time.

Effects of the Invention As described above, according to the digital signal storage device of the present invention, by using N (an integer of 3 or more) serial input serial output type shift registers, the writing speed of the corresponding memory can be adjusted by changing the writing speed of the shift register. The speed can be reduced to 1/(N-1) of the speed. As a result, a high-speed, large-capacity storage device can be obtained. The number of bits in each shift register is preferably an integral multiple (including 1) of (N-1). In addition, the shift register can be controlled by simply changing the clock frequency.
The configuration of the entire device becomes simple.

Modifications to the Embodiments Although only preferred embodiments of the invention have been described above, those skilled in the art will appreciate that various modifications can be made without departing from the spirit of the invention. For example, the clock generating means 20 may generate a clock signal that is synchronized with a digital input signal or whose frequency is variable. The gate 32 may be a NAND gate or a digital switch other than an AND gate. Also, a reset circuit may be provided to reset each block when starting to store digital input signals, and at that time, the count value of each counter may be appropriately preset so that input signals can be stored from the first address. Good too. Semiconductor in memory
In addition to IC RAM, core memory, magnetic disk,
A magnetic tape or the like may also be used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a preferred embodiment of the present invention, and FIG. 2 is a time chart explaining the operation of FIG. 12-1 to 12-4: Shift register, 14
-1 to 14-4: Selection means, 18-1 to 18-
4: Memory, 20: Clock generation means, 26: Control means.

Claims (1)

[Claims] 1. N serial-input serial-output shift registers (N is an integer of 3 or more) to which a digital input signal is commonly supplied; clock generation means for generating a second clock signal of a certain frequency; selection means for selectively supplying the first and second clock signals to the N shift registers; and digital outputs of the N shift registers. N memories each receiving a signal, and control means for controlling a write operation of the memories and a selection operation of the selection means, and under the control of the control means, the selection means selects the N shift registers. Only one of the above
The digital input signal is newly stored in all the bits of the one shift register that supplies the clock signal and also supplies the second clock signal to the other shift register and receives the first clock signal. Each time, the one shift register receiving the first clock signal is replaced in sequence, and only the memory corresponding to the shift register receiving the second clock signal is subjected to a write operation. Digital signal storage device.