JPS63276270A - Manufacture of radiation resistant semiconductor device - Google Patents
Manufacture of radiation resistant semiconductor deviceInfo
- Publication number
- JPS63276270A JPS63276270A JP11191987A JP11191987A JPS63276270A JP S63276270 A JPS63276270 A JP S63276270A JP 11191987 A JP11191987 A JP 11191987A JP 11191987 A JP11191987 A JP 11191987A JP S63276270 A JPS63276270 A JP S63276270A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- nitriding
- temperature
- radiation
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005855 radiation Effects 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000005121 nitriding Methods 0.000 claims abstract description 12
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 6
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000006303 photolysis reaction Methods 0.000 claims description 2
- 230000015843 photosynthesis, light reaction Effects 0.000 claims description 2
- 230000002285 radioactive effect Effects 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 238000006243 chemical reaction Methods 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 abstract description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置、特にシリコンMOS半導体装置
の耐放射線性の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improving the radiation resistance of semiconductor devices, particularly silicon MOS semiconductor devices.
宇宙空間、原子炉周辺などに半導体集積回路を使用する
場合には、放射線損傷を受けやすいので、耐放射線性の
向上が図られている。When semiconductor integrated circuits are used in outer space, around nuclear reactors, etc., they are susceptible to radiation damage, so efforts are being made to improve their radiation resistance.
高集積度を有する半導体集積回路の基本素子であるMO
S)ランジスタでは、放射線損傷はしきい値電圧の変動
、リーク電流の増加として現われ特性劣化を生ぜしめる
。この劣化の原因は、放射線がゲート絶縁酸化膜に入射
して生じた多量の電子・正孔対が一部は再結合で消滅す
るが、一部はシリコン酸化膜に捕獲され、特に正孔が移
動度が小さいため捕獲式れ易く、シリコン酸化膜内に正
の固定電荷を、またシリコン酸化膜/シリコン基板の界
面に捕獲され界面準位を形成するためだといわれている
。MO is a basic element of semiconductor integrated circuit with high degree of integration.
S) In transistors, radiation damage appears as a change in threshold voltage and an increase in leakage current, causing characteristic deterioration. The cause of this deterioration is that a large number of electron-hole pairs generated when radiation enters the gate insulating oxide film are partially annihilated by recombination, but some are captured by the silicon oxide film, and holes in particular are It is said that this is because it is easily captured due to its low mobility, and it creates positive fixed charges within the silicon oxide film and is trapped at the silicon oxide film/silicon substrate interface to form an interface state.
上記の放射線損傷の程度は、ゲート絶縁酸化膜の形成法
およびその後の熱処理過程によって、大きく変化し、経
験的に低温製造プロセスで製造した装置の耐放射線性が
良いことがわかっている。また、シリコン酸化膜を高温
で熱窒化すれば良いとの報告もめる。The degree of radiation damage described above varies greatly depending on the method of forming the gate insulating oxide film and the subsequent heat treatment process, and it has been empirically found that devices manufactured using low-temperature manufacturing processes have good radiation resistance. There are also reports that thermal nitridation of silicon oxide films at high temperatures is sufficient.
しかしながら、耐放射線向上のための低温製造プロセス
は、改善の効果があまシ大きくなく、さらに耐性の向上
をはかる必要がある。また高温熱窒化法は、シリコン酸
化膜をアンモニアふんい気中で、1000C以上の高温
で数時間にわたって熱窒化するものであるが、界面準位
発生量は減少するものの固定正電荷蓄積量は逆に増加し
、MOS)ランジスタのしきい値電圧が大きく変動する
。However, the low-temperature manufacturing process for improving radiation resistance does not have a significant improvement effect, and it is necessary to further improve the resistance. In addition, in the high-temperature thermal nitriding method, a silicon oxide film is thermally nitrided in an ammonia atmosphere at a high temperature of 1000 C or more for several hours, but although the amount of interface states generated decreases, the amount of fixed positive charge accumulation is the opposite. , and the threshold voltage of the MOS transistor changes greatly.
本発明の目的は、上記の事情に鑑み、従来の方法に対し
優れた耐放射性をうろことのできる製造方法を提供する
ことにある。In view of the above circumstances, an object of the present invention is to provide a manufacturing method that can achieve radiation resistance superior to conventional methods.
本発明の方法は、ゲート絶縁酸化膜形成後、半導体基板
を前記ゲート絶縁酸化膜の熱酸化温度以下に保ち、前記
ゲート絶縁酸化膜の少なくとも一部を窒化するようにし
たものである。窒化の方法は、アンモニアふんい気中で
、紫外線照射による光分解、もしくは高温短時間のラン
プ加熱によることができる。In the method of the present invention, after forming a gate insulating oxide film, the semiconductor substrate is maintained at a temperature below the thermal oxidation temperature of the gate insulating oxide film, and at least a portion of the gate insulating oxide film is nitrided. The nitriding method can be carried out by photolysis by ultraviolet irradiation in an ammonia atmosphere or by lamp heating at high temperature for a short time.
高温熱窒化法では、酸化膜の窒化によシ界面準位発生量
は減少するが、固定正電荷蓄積量が逆に増大した。これ
は、高温による熱ストレスによシ正孔の捕獲確率が増大
するためと考えられるが、本発明では低温において窒化
するので後者の不都合を防ぐことができる。一方窒化に
よる効果としてシリコン酸化膜/シリコン基板界面に薄
い窒化膜層が形成され界面準位発生量を減少させ、さら
にシリコン酸化膜表面あるいは内部に存在する窒素が再
結合中心として働くので固定正電荷蓄積量を減少させる
ことができる。低温窒化であるから、ゲート絶縁酸化膜
は、金膜が必ずしも窒化しないが、一部でも効果がある
。In the high-temperature thermal nitriding method, the amount of interface states generated decreased due to nitriding of the oxide film, but the amount of fixed positive charge accumulation increased. This is thought to be because the probability of trapping holes increases due to thermal stress caused by high temperatures, but in the present invention, since nitridation is performed at low temperatures, the latter disadvantage can be prevented. On the other hand, as an effect of nitriding, a thin nitride film layer is formed at the silicon oxide film/silicon substrate interface, reducing the amount of interface states generated, and nitrogen existing on or inside the silicon oxide film acts as a recombination center, so there is a fixed positive charge. The amount of accumulation can be reduced. Since low-temperature nitridation is used, the gold film in the gate insulating oxide film is not necessarily nitrided, but even a portion of the gate insulating oxide film is effective.
以下、本発明の一実施例につき説明する。実施例は、P
Wシリコン基板上に、素子分離酸化膜によ)分離された
素子がポリシリ=7ゲートトランジスタである集積回路
を対象とする。第1図は、トランジスタ構造形成までの
工程を図示した断面図である。第1図(a)は分離用の
厚いシリコン酸化膜1oz、チャネルストッパ103が
シリコン基板101に形成された状態を示す。次に、第
1図(b)に示すように、反応容器105内で1ooo
c以下、例えば950 Cで膜厚10〜500 nmの
ゲート絶縁酸化膜104を形成する。106は加熱用ヒ
ータで、シリコン基板101を搭載し、反応中温度を一
定化している。以上の酸化工程を終えると、反応容器1
05をアンモニアふんい気に置換え、シリコン基板10
1の温度は950C以下の、例えば900Cに保ってお
き、低圧水銀灯で紫外線(λ=185nm ) 107
を照射し、窒化反応を行なう。光照射はレーザ光、例え
ばArFエキシマレーザ(λ=193nm)で行なって
もよい。An embodiment of the present invention will be described below. Examples are P
The present invention is directed to an integrated circuit in which the elements separated (by an element isolation oxide film) on a W silicon substrate are polysilicon 7-gate transistors. FIG. 1 is a cross-sectional view illustrating the steps up to the formation of a transistor structure. FIG. 1A shows a state in which a 1 oz thick silicon oxide film for isolation and a channel stopper 103 are formed on a silicon substrate 101. Next, as shown in FIG. 1(b), 1ooo
A gate insulating oxide film 104 having a thickness of 10 to 500 nm is formed at a temperature of 950 C or less, for example. Reference numeral 106 denotes a heating heater, on which the silicon substrate 101 is mounted, and keeps the temperature constant during the reaction. After completing the above oxidation process, reaction vessel 1
05 was replaced with ammonia, and a silicon substrate 10 was prepared.
The temperature of step 1 is kept below 950C, for example 900C, and UV light (λ=185nm) is applied using a low pressure mercury lamp.
is irradiated to perform a nitriding reaction. The light irradiation may be performed using a laser beam, for example, an ArF excimer laser (λ=193 nm).
第1図(e)以降はNチャネルMOS)ランジスタの各
電極を形成する工程でおる。先ず第1図(C)に示すよ
うに、リンを含有するポリシリコンゲート電極108t
−公知の蝕刻技術で形成し、次に第1図(d)に示すよ
うに、ポリシリコンゲート電極108の側面酸化109
を行なった後、砒素等のイオン注入によりソース領域1
10.ドレイン領域111を形成する。その後保護絶縁
膜を全面に被着後、ソース・ゲート電極を形成し、トラ
ンジスタが完成する。The steps from FIG. 1(e) onwards are steps for forming each electrode of an N-channel MOS transistor. First, as shown in FIG. 1(C), a polysilicon gate electrode 108t containing phosphorus is formed.
- formed by known etching techniques and then oxidized 109 on the sides of the polysilicon gate electrode 108, as shown in FIG. 1(d).
After performing this, the source region 1 is implanted with ions such as arsenic.
10. A drain region 111 is formed. A protective insulating film is then deposited over the entire surface, and source and gate electrodes are formed to complete the transistor.
第2図に従来の低温製造プロセスによるMOSトランジ
スタ(破線で示す)と本発明の窒化処理を行なったMO
S)ランジスタ(実線で示す)との放射線照射前後のサ
ブスレッショルド特性の一例を示す。初期特性はほぼ等
しいが、放射線照射後の負方向へのシフト量、サブスレ
ッショルドスイングの変動はいずれも本発明の窒化処理
を行なったMOS)ランジスタが小さいことがわかる。Figure 2 shows a MOS transistor (indicated by a broken line) manufactured by a conventional low-temperature manufacturing process and a MOS transistor manufactured by the nitriding process of the present invention.
S) An example of subthreshold characteristics before and after radiation irradiation with a transistor (indicated by a solid line) is shown. It can be seen that although the initial characteristics are almost the same, the amount of shift in the negative direction and the fluctuation of the subthreshold swing after radiation irradiation are both smaller in the MOS transistor subjected to the nitriding treatment of the present invention.
以上の結果は固定正電荷の蓄積と界面−位の発生がとも
に小さいことを示している。The above results indicate that both the accumulation of fixed positive charges and the generation of interface potentials are small.
低温窒化の方法として、第1図(b)に示す紫外線照射
に変えて、アンモニアふんい気で、10秒〜5分の短時
間の高温(1000〜1200 C)ランプ加熱を行な
い反応を生ぜしめるようにしてもよい。このときシリコ
ン基板は熱酸化温度以下の温度に保つ。上記の方法を、
第1図と同様のP型シリコン基板上のポリシリコンゲー
トトランジスタに適用した結果は略々同様の効果を得、
放射線損傷が少ない。As a low-temperature nitriding method, instead of the ultraviolet irradiation shown in Figure 1(b), short-term high-temperature (1000-1200 C) lamp heating is performed in ammonia atmosphere for 10 seconds to 5 minutes to cause a reaction. You can do it like this. At this time, the silicon substrate is kept at a temperature below the thermal oxidation temperature. The above method,
When applied to a polysilicon gate transistor on a P-type silicon substrate similar to that shown in Fig. 1, almost the same effect was obtained.
Less radiation damage.
以上説明したように、本発明はゲート絶縁酸化膜を熱酸
化温度以下の低温で窒化を行なうことによって、放射線
により生ずるシリコン酸化膜中の蓄積固定正負荷、シリ
コン酸化膜/シリコン基板界面に発生する界面準位の増
大を、従来に対し大幅に減少させることができる。As explained above, the present invention nitrides the gate insulating oxide film at a low temperature below the thermal oxidation temperature, thereby eliminating the fixed positive load accumulated in the silicon oxide film caused by radiation and generated at the silicon oxide film/silicon substrate interface. The increase in interface states can be significantly reduced compared to the conventional method.
第1図は、本発明の一実施例を示す断面図、第2図は従
来法と実施例とによシ製作したMOSトランジスタの耐
放射性特性を示す図である。
101・・・シリコン基板、
102・・・シリコン酸化膜(素子分離用)、103・
・・チャネルストッパ、
104・・・ゲート絶縁酸化膜、
105・・・反応容器、
106・・・加熱用ヒータ、
107・・・紫外線。FIG. 1 is a cross-sectional view showing an embodiment of the present invention, and FIG. 2 is a diagram showing radiation resistance characteristics of MOS transistors manufactured by the conventional method and the embodiment. 101...Silicon substrate, 102...Silicon oxide film (for element isolation), 103...
...Channel stopper, 104...Gate insulating oxide film, 105...Reaction vessel, 106...Heating heater, 107...Ultraviolet rays.
Claims (2)
酸化膜形成後、半導体基板を前記ゲート絶縁酸化膜の熱
酸化温度以下に保ち、前記ゲート絶縁酸化膜の少なくと
も一部を窒化することを特徴とする耐放射線性半導体装
置の製造方法。(1) In a silicon MOS semiconductor device, after forming a gate insulating oxide film, the semiconductor substrate is maintained at a temperature below the thermal oxidation temperature of the gate insulating oxide film, and at least a part of the gate insulating oxide film is nitrided. A method for manufacturing a radioactive semiconductor device.
射による光分解、もしくは高温短時間のランプ加熱によ
る特許請求の範囲第1項記載の耐放射線半導体装置の製
造方法。(2) The method for manufacturing a radiation-resistant semiconductor device according to claim 1, wherein the nitriding is carried out by photolysis by ultraviolet irradiation or lamp heating at high temperature and for a short time in an ammonia atmosphere.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62111919A JPH063810B2 (en) | 1987-05-08 | 1987-05-08 | Method for manufacturing radiation resistant semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62111919A JPH063810B2 (en) | 1987-05-08 | 1987-05-08 | Method for manufacturing radiation resistant semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63276270A true JPS63276270A (en) | 1988-11-14 |
JPH063810B2 JPH063810B2 (en) | 1994-01-12 |
Family
ID=14573403
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62111919A Expired - Lifetime JPH063810B2 (en) | 1987-05-08 | 1987-05-08 | Method for manufacturing radiation resistant semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH063810B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0422128A (en) * | 1990-05-17 | 1992-01-27 | Sharp Corp | Nitriding treatment method of silicon oxide film |
JP2016127194A (en) * | 2015-01-07 | 2016-07-11 | 株式会社Screenホールディングス | Heat treatment method and heat treatment device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55113335A (en) * | 1979-02-23 | 1980-09-01 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1987
- 1987-05-08 JP JP62111919A patent/JPH063810B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55113335A (en) * | 1979-02-23 | 1980-09-01 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0422128A (en) * | 1990-05-17 | 1992-01-27 | Sharp Corp | Nitriding treatment method of silicon oxide film |
JP2016127194A (en) * | 2015-01-07 | 2016-07-11 | 株式会社Screenホールディングス | Heat treatment method and heat treatment device |
Also Published As
Publication number | Publication date |
---|---|
JPH063810B2 (en) | 1994-01-12 |
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