JPH05102482A - Structure of pmosfet and its manufacturing method - Google Patents

Abstract

PURPOSE:To form a PMOSFET in less manhours, in excellent yield rate, and at low cost by enabling the formation of a p-layer for forming gate drain overlap structure to be executed by thermal diffusion. CONSTITUTION:A gate SiO2 film 15 is made as a gate insulating film on an n-type silicon substrate 11. The section being one part of the gate SiO2 film and the channel planned area of the board 11 is changed into a insulating oxynitride film 21 by being nitrided by N2O or NH3. And a gate electrode 27 is made, which contains p-type impurities so that it may cover the insulating oxynitride film 21 and jut out over to the gate SiO2 film 15 parts on both sides in the longitudinal direction of a channel. And, BF2 ions are implanted and annealed, and p-type impurities 37 are diffused from the gate electrode 27 to the board 11 so as to form a p-type diffusion layer 39. What is more, boron 37 passes the gate SiO2 film 15 and diffuses into the board 11, but the oxynitride film 12 checks the passage of boron 37, so boron does not diffuse to the board 11 below it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a MIS field effect transistor, especially a PMOSFET, and a manufacturing method thereof.

[0002]

2. Description of the Related Art P ^{+ using} P ⁺ polysilicon as a gate electrode
Also in MOSFETs, element deterioration due to hot carriers has become a problem with the miniaturization of elements.

Therefore, in order to prevent the generation of hot carriers, the inventor, like the NMOSFET, has the PMOSFET.
We also considered using a gate / drain overlap structure.

Conventionally, the adoption of a gate / drain overlap structure in an NMOSFET has been described in a publication of the Institute of Electronics and Electrical Engineers (IEEE IEDM Tech. Di.
g. , Pp 38-41, 1987).
The structure disclosed in this document is shown in FIGS. 2A and 2B in a sectional view of the main part. FIG. 2A shows a conventional structure, in which the sidewalls are mainly on the N ⁻ layer. On the other hand, FIG. 2B shows an improved structure of the related art, in which the gate electrode is extended to the upper part of the N ⁻ layer for high reliability,
Has a high driving ability.

It should be noted that in FIG.
0, the N ⁺ layer 112, the N ⁻ layer 114, the gate insulating film 116, the upper portion of the gate electrode 118 a, the lower portion thereof 118 b, and the sidewall 120.

As the gate insulating film, SiO _{2 obtained} by oxidizing a silicon substrate has been conventionally used, but an example thereof is a document (IEEE IEDM Tech. Di.
g. , Pp425-428, 1990). The structure disclosed in this document is shown in cross section in FIG. According to this structure, after forming SiO _{2 of the} gate insulating film on the substrate 130, nitrous oxide (N ₂ O) is further formed.
Alternatively, an oxynitride insulating film 132 nitrided with ammonia (NH ₃₎ has been proposed. This oxynitride insulating film 132 is reported to have higher reliability against electric stress than a conventional SiO ₂ film. Reference numeral 134 is a gate electrode, 136 is an impurity ion of boron (B) contained in the gate electrode 134, and 138 is an N ⁺ layer.

By the way, SiO is usually used as a gate insulating film.
_{Since the two} films are used, in the PMOSFET using P ⁺ polysilicon as the gate electrode, the phenomenon that boron, which is an impurity present in the gate electrode, penetrates into the substrate occurs. This penetration of boron occurs due to the high diffusion rate of boron, and this penetration results in PMO.
The characteristics of the SFET will change.

However, this document shows that such a punch-through phenomenon is suppressed by nitriding the gate oxide film. This point will be briefly described below.

That is, FIG. 4 (FIG. 4 shows FIG.
) From experimental data showing the results of analysis of the depth and boron concentration from the substrate surface by SIMS (Secondary Ionization Mass Spectroscopy). I know there isn't. On the other hand, from the data I of the sample not subjected to the nitriding treatment, 1.0 × 10 ¹⁷ (1.0 × 10 17)
It can be seen that boron atoms of about (atoms / cm ³ (cm cubed)) are penetrating.

FIG. 5 (FIG. 5 is referred to in FIG.
(Quoted from (a)) shows curves I and II of the gate voltage and the drain current for the PMOSFET with drain voltages Vd = −3.0 V and Vd = −0.1 V, respectively. From II,
It can be seen that the P ⁺ polysilicon gate PMOSFET which has been oxynitrided with N ₂ O exhibits good transistor characteristics.

[0011]

[Problems to be Solved by the Invention] However, the PMO
Since the manufacturing process of adopting the gate / drain overlap structure for the SFET is technically complicated, the number of steps increases, and there are problems in terms of cost and yield.

Therefore, the present invention provides a manufacturing method and a structure for solving the above problems.

[0013]

In order to achieve this object, according to the structure of the PMOSFET of the present invention, the gate is formed by providing a gate electrode of P ⁺ polysilicon on the ground with a gate insulating film interposed. It is characterized by adopting a gate / drain overlap structure in which a part of the insulating film is an oxynitride insulating film.

Further, according to the method of manufacturing a PMOSFET of the present invention, (a) a step of forming a gate oxide film as a gate insulating film on the underlayer, and (b) a part of the gate oxide film, wherein the underlayer is formed. And (c) covering the oxynitride insulating film on a portion of the planned channel region that will be the channel of (1) and covering the oxynitride insulating film on the gate oxide film portions on both sides in the channel length direction from the oxynitride insulating film. P to stick out
Forming a gate electrode containing type impurities,
(D) During annealing after the step (c), the P from the gate electrode through the gate oxide film portion into the base layer
Diffusing a type impurity to form a P ⁻ type diffusion layer in the underlayer.

In carrying out the present invention, preferably, the step (b) of claim 2 is performed by nitriding the gate oxide film with nitrous oxide (N ₂ O) or ammonia (NH ₃ ), The P-type impurity is preferably boron (B).

[0016]

According to the above-described structure of the present invention, the gate oxide film portion having a length shorter than the gate length is changed to the oxynitride insulating film on the lower side of the gate electrode and on the central side of the gate electrode. There is. Therefore, the gate insulating film is composed of this oxynitride insulating film and the gate oxide film portions on both sides in the gate length direction. This oxynitride insulating film has a function of stopping movement of P-type impurities in the gate electrode due to thermal diffusion.

Therefore, the P ⁻ layer for forming the gate / drain overlap structure is formed by thermally diffusing from the gate electrode to the base through the gate oxide film portion at a required annealing step after the gate electrode is formed. can do.

As described above, according to the present invention, since the P ⁻ layer can be formed by thermal diffusion without using ion implantation, the number of manufacturing steps is smaller than in the conventional case, and the gate insulating film is not damaged. Moreover, it is possible to manufacture at low cost and with good yield by combining ordinary techniques.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that this figure merely schematically shows the shapes, dimensions, and positional relationships of the respective constituent components to the extent that the present invention can be understood. Further, in the drawings, hatching and the like showing the cross section are partially omitted.

In the following description, the PMO of the present invention will be described.
The method of manufacturing the SFET will be mainly described, and the structure of the PMOSFET can also be easily understood by this description, and thus redundant description will be omitted.

1 (A) to 1 (E) show a PMOSFET (P) having a gate / drain overlap structure of the present invention.
Type MOS field effect transistor) is a process diagram for explaining an embodiment of a method for manufacturing the same, and each structure shows a structure obtained in a main process step by a cross section.

First, in this description, a gate oxide film is formed as a gate insulating film on the base. Therefore, in this embodiment, an N-type silicon (Si) substrate 11 is prepared as a base. Then, a field oxide film 13 is formed on the N-type silicon substrate 11 by a normal element isolation method. next,
A gate SiO ₂ film 15 is formed as a gate insulating film on the surface of the substrate to be an active region by a method such as thermal oxidation or CVD so as to have a film thickness of 6 nm, for example. The structure thus formed is shown in FIG.

Next, in the present invention, a part of the SiO ₂ film 15 which is the gate oxide film is changed to the oxynitride insulating film 21. Therefore, a film, for example, a polysilicon film 17, which serves as a mask at the time of nitriding later is deposited on the entire upper surface of the structure of FIG.

Then, using the usual photolithography and etching techniques, the MOS of the substrate 11 as a base is formed.
The opening 19 is formed by removing the portion of the polysilicon film located above the planned channel region of the FET.

After that, by nitriding the gate SiO ₂ film portion exposed in the opening 19 in an N ₂ O or NH ₃ atmosphere, this SiO ₂ film is changed to the oxynitride insulating film 21 and, as shown in FIG. A structure as shown in B) is obtained.

In the figure, the gate oxide film portion left as SiO _{2 by} this nitriding treatment is also indicated by 15.

Next, in the present invention, the gate electrode 27 containing P-type impurities is formed. Therefore, first, all the polysilicon film 17 provided in the previous step is removed. After that, a polysilicon film is again deposited on the entire surface, and any suitable ion that acts as a P-type impurity on the polysilicon film,
For example, BF ₂ ions (boron fluoride ions) 23 are implanted to contain boron (B), thereby forming a P ⁺ polysilicon film 25. Figure 1 shows the structure in this state.
(C) of.

Next, the P ⁺ polysilicon layer 25 is patterned to form a gate electrode 27. At this time P
The gate electrode 27 containing a type impurity is the oxynitride insulating film 21.
Is formed so as to cover the upper side of the gate insulating film 21 and extend in the gate length direction so as to extend from the oxynitride insulating film 21 to a part of the gate SiO ₂ film.

Then, BF ₂ ions 29 are implanted using the field oxide film 13 and the gate electrode 27 as a mask to form P ⁺ regions (source / drain regions) 31a and 31b in the substrate 11, respectively. .. The resulting structure is shown in FIG.

Next, in the present invention, the P-type impurity 37 is diffused from the gate electrode 27 into the substrate 11 by annealing.

In the process of this embodiment, subsequent to the formation of the P ⁺ region, annealing for source / drain activation is performed for 30 minutes at a temperature of about 900 ° C. in a nitrogen atmosphere, for example. By this high-temperature annealing, boron (B) 37 as a P-type impurity passes through the gate SiO ₂ film portion 15 and diffuses into the substrate 11, but the oxynitride insulating film 21 passes through this boron (B) 37. Since it blocks, boron does not diffuse into the region of the substrate 11 below the oxynitride insulating film 21.

Then, after forming the insulating film 33, a contact hole is opened. Here, when forming the insulating film 33 and the contact hole, a high temperature heat treatment (for example, 900
Annealing is performed twice at 20 ° C. for 20 minutes. The P ⁻ diffusion layer is formed by the series of annealing. After that, the Al (aluminum) wiring 35 is formed by a normal vapor deposition method. The structure of the PMOSFET manufactured in this manner is shown in FIG.

The structure of this PMOSFET comprises a P ⁺ silicon gate electrode 27 with a gate insulating film (15, 21) interposed on a substrate 11 as a base, and a part of this gate insulating film is oxynitride insulating. It is a membrane 21 and has a gate-rain overlap structure as a whole.

According to the above-described embodiment of the present invention, after the gate electrode is formed, the high temperature treatment is performed several times until the MOSFET is completed. At this time, as described above, the boron 37, which is an impurity in the gate electrode 27, penetrates the gate SiO ₂ film portion 15 and the silicon substrate 1
1 to form a P ⁻ diffusion layer 39. Therefore, in the present invention, special heating for forming the P ⁻ diffusion layer 39 need not be performed.

Further, as already described in the section of the prior art,
Since the oxynitride insulating film 21 can suppress the penetration of boron, boron does not diffuse into the region of the silicon substrate 11 below the oxynitride insulating film 6. Therefore, no impurities have diffused or entered the planned channel region, and therefore the PMOS
Does not deteriorate the characteristics of the FET.

Then, by the series of steps of the present invention described above, the PMOS of the gate / drain overlap structure is formed.
The FET can be easily formed at low cost.

[0037]

As is apparent from the above description of the present invention, according to the structure of the PMOSFET of the present invention and the manufacturing method thereof, the P ⁻ layer can be formed without ion implantation, and the number of steps is reduced. ^- formation of layers rather than by ion implantation, since it is formed by diffusion, P
^- no damage to the gate insulating film on the layer, and
It is possible to obtain an advantage that it can be easily formed by a combination of conventional techniques without using a complicated and sophisticated technique.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a PMOSFET having a gate / drain overlap structure according to the present invention.

FIG. 2 is an explanatory diagram of a gate / drain overlap structure.

FIG. 3 is an explanatory diagram illustrating the penetration of boron in a P ⁺ silicon layer into a substrate.

FIG. 4 is a graph showing the boron concentration by SIMS at the substrate depth.

FIG. 5 is a graph showing transistor characteristics of P ⁺ polysilicon gate PMOSFET subjected to oxynitriding treatment.

[Explanation of symbols]

11 N-type silicon substrate 13 Field oxide film 15 Gate SiO ₂ film 17 Polysilicon film 19 Opening 21 Oxynitride insulating film 23 BF ₂ ion 25 P ⁺ polysilicon film 27 Gate electrode 29 BF ₂ ion 31a P ⁺ diffusion layer (source) -Drain region) 31b P ⁺ diffusion layer (source / drain region) 33 Insulating film 35 Al (aluminum) wiring 37 B (boron) 39 P ^- diffusion layer

Claims (4)

[Claims] 1. A P ⁺ layer with a gate insulating film interposed on the lower ground.
A PMOSFET having a gate-drain overlap structure in which a part of the gate insulating film provided with a polysilicon gate electrode is used as an oxynitride insulating film.
Structure. 2. The method for manufacturing a PMOSFET according to claim 1, wherein (a) a step of forming a gate oxide film as a gate insulating film on the underlayer, and (b) a part of the gate oxide film, A step of changing a portion on the planned channel region which becomes the underlying channel into an oxynitride insulating film, and (c) a gate oxide film portion covering the oxynitride insulating film and on both sides of the oxynitride insulating film in the channel length direction. A step of forming a gate electrode containing a P-type impurity so as to protrude above, and (d) during annealing after the step (c), from the gate electrode through the gate oxide film portion into the base layer.
And a step of diffusing a type impurity to form a P ⁻ type diffusion layer in the underlayer. 3. The manufacturing method according to claim 2, wherein the gate oxide film is nitrided with nitrous oxide (N ₂ O) or ammonia (NH ₃ ). 4. The manufacturing method according to claim 2, wherein the P-type impurity is boron (B).