JP2738327B2 - Method for manufacturing MOS type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a MOS type semiconductor device, and more particularly to a method for manufacturing a CMOS integrated circuit having both an n-channel transistor and a p-channel transistor.

[0002]

2. Description of the Related Art As the miniaturization of a MOS type semiconductor device progresses, the electric field strength of a drain increases, so that hot electrons are generated, thereby generating a new electron-hole pair. Is injected into the gate oxide film, and the transistor is significantly deteriorated. In order to prevent this, in an n-channel transistor, a so-called LDD (Light Weight) in which an n ⁻ type diffusion layer is formed in a region near a gate.
It has become common to adopt a tly doped drain structure.

However, in a p-type transistor, the influence of hot carriers is not so remarkable as in an n-type transistor. When an LDD structure is adopted, a source resistance is increased and a high-speed operation is hindered. Therefore, it is desirable to have a single drain structure. Therefore, in a CMOS integrated circuit in which an n-channel transistor and a p-channel transistor are mixed, it is necessary to form a transistor having an LDD structure and a transistor having a single drain structure.

FIGS. 5 (a) to 5 (d) and FIGS. 6 (a) to 6 (c)
Is a process order sectional view showing a conventional method for manufacturing this type of semiconductor device. First, as shown in FIG. 5A, after forming an n-well 302 and a p-well 303 on a p-type semiconductor substrate 301, a field oxide film 304 is formed by a selective oxidation method. Next, after a gate oxide film 305 is formed by thermal oxidation, a polysilicon film 306 having a thickness of about 0.3 μm is formed on the gate oxide film.

The polysilicon film 306 desirably contains phosphorus (P). Next, as shown in FIG. 5B, after a gate electrode 307 is formed using a photolithography technique and a dry etching technique, an n-type impurity such as phosphorus is added to the substrate at an acceleration energy of 50 to 100 k.
eV, dose: 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁴ cm ⁻²
The n ^- type diffusion layer 311 is formed under such conditions.
Subsequently, as shown in FIG.
Silicon oxide film 3 on the entire surface by apor deposition
08 is formed to a thickness of about 0.1 to 0.2 μm, and then anisotropically etched to form sidewalls 308 a on both sides of the gate electrodes 307 of the n-channel and p-channel transistors as shown in FIG. To form

Next, as shown in FIG. 6A, an n-type impurity, for example, arsenic is selectively introduced into the n-channel transistor forming region using the photoresist film 309 as a mask, at an acceleration energy of 70 to 100 keV and a dose of: 1.0-5.
The n-type transistor is introduced under the condition of about 0 × 10 ¹⁵ cm ⁻² to form an n ⁺ -type diffusion layer 310 serving as a source / drain region, and the n-channel transistor has an LDD structure.

Next, as shown in FIG. 6B, a p-type impurity, for example, boron fluoride (BF) is selectively formed in the p-channel transistor formation region using the photoresist film 312 as a mask.
₂ ^+), acceleration energy: 70～100KeV, dose: 1.0 to 5.0 × 10 ¹⁵ introduced in cm ^-2 order of conditions, to form a p ⁺ -type diffusion layer 313 serving as source and drain regions. Here, since the p-channel transistor is a single drain transistor with a sidewall, it has an offset structure.

Therefore, as shown in FIG. 6C, a heat treatment is performed in a nitrogen atmosphere at 900 ° C. for about 20 to 30 minutes to diffuse the p ⁺ -type diffusion layer 313 deeply and to overlap the end of the gate electrode. Wrap and eliminate the offset structure. A method of manufacturing a conventional MOS type semiconductor device of this type is known, for example, from Japanese Patent Application Laid-Open No. 2-22862.

[0009]

In the above-described conventional manufacturing method, high-temperature heat treatment is performed after impurity implantation into the source / drain in order to prevent the source / drain region of the p-channel transistor from having an offset structure. It is necessary. However, this heat treatment causes a problem that a deeply and widely formed diffusion layer having a high impurity concentration significantly deteriorates element isolation characteristics.

SUMMARY OF THE INVENTION The present invention has been made in view of this point, and an object of the present invention is to provide a MOS type semiconductor device having an n-channel transistor having an LDD structure and a p-channel transistor having a single drain structure, and An object is to eliminate the offset structure of a p-channel transistor without deteriorating the isolation characteristics.

[0011]

According to the present invention, there is provided, according to the present invention, (1) on a first active region made of a p-type semiconductor and on a second active region made of an n-type semiconductor, respectively. A step of forming a gate electrode via a gate insulating film; (2) a step of covering a side surface of the gate electrode with a mask forming material layer serving as a spacer over the entire surface of the semiconductor substrate; (3) Covering the second active region with a first mask body; and (4) using the first mask body, the gate electrode, and the mask forming material layer applied to side surfaces of the gate electrode as a mask. ion-implanting an n-type impurity to form a source / drain region having a high impurity concentration in a surface region of the first active region separated from the gate electrode; and (5) forming the first mask body and The mask (6) n-type impurities are introduced using the gate electrode as a mask, and n-type impurities having a low impurity concentration are formed in the surface regions of the first and second active regions adjacent to the gate electrode. Forming a type diffusion layer; (7) covering the first active region with a second mask; and (8) p-type impurities using the second mask and the gate electrode as a mask. Is introduced deeper than the depth of the n-type diffusion layer having a low impurity concentration, so that a source region having a high impurity concentration is formed in a surface region of the second active region adjacent to the gate electrode.
Forming a drain region.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIGS. 1A to 1C and FIGS.
(C) is a sectional view in order of process for explaining the first example of the present invention. First, as shown in FIG. 1A, an n-well 102 and a p-well 103 are formed on a p-type semiconductor substrate 101.
Is formed, a field oxide film 10 is formed by a selective oxidation method.
4 is formed. Subsequently, the gate oxide film 10 is thermally oxidized.
After the formation of the polysilicon film 5, a polysilicon film 106 having a thickness of about 0.3 μm is formed by the CVD method.

Next, as shown in FIG. 1B, the polysilicon film 106 is formed by photolithography and RIE.
(Reactive Ion Etching) method is used to form the gate electrode 107, and the entire surface of the silicon oxide film 108 containing phosphorus is deposited by CVD to a thickness of 0.1 to 0.2 μm.
The thickness is about m.

Next, as shown in FIG. 1C, the n-well 102 is covered with a photoresist film 109 by applying a photolithography technique, and the gate electrode 107 and the silicon oxide film previously formed are covered with the photoresist film 109. Using 108 as a mask, an n-type impurity, for example, arsenic, at an acceleration energy of 250 to 300 sufficient to allow the silicon oxide film to pass through
keV, dose: was introduced to the p-well 103 in 1.0~5.0 × 10 ¹⁵ cm ^-2 order of conditions, to form an n ⁺ -type diffusion layer 110 in the source and drain formation regions of the n-channel transistor. At this time, since the silicon oxide film 108 is formed thick on the side of the gate electrode 107, the n ⁺ -type diffusion layer 110 is not formed in this region.

After removing the photoresist film 109 and removing the entire surface of the silicon oxide film 108 by isotropic etching, as shown in FIG. 2A, an n-type impurity such as phosphorus is accelerated at an acceleration energy of 50 to 100 keV. , Dose:
By introducing the entire surface under the condition of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁴ cm ⁻² , the n ⁻ -type diffusion layer 111 is formed in the source / drain formation region including the gate electrode side portions of both transistors.
To form Thus, an n-channel transistor having an LDD structure can be formed.

Next, as shown in FIG. 2B, the p-well 103 is covered with a photoresist film 112 by applying a photolithography technique, and this and the previously formed gate electrode 107 are used as a mask. , A p-type impurity, for example, boron fluoride, is introduced under the conditions of an acceleration energy of 70 to 100 keV and a dose of about 1.0 to 5.0 × 10 ¹⁵ cm ^−2, so that the source / drain region of the p-channel transistor is The p ⁺ type diffusion layer 113 is formed. Thus, a p-channel transistor that does not have an offset structure can be formed.

After removing the photoresist film 112, as shown in FIG. 2C, the BPSG (Bo
An interlayer insulating film 114 made of, for example, ro-phospho-silicate glass) is formed, and a heat treatment for reflow is performed. As a result, the activation of the previously implanted impurities is also performed at the same time. That is, heat treatment for indenting the p ⁺ -type diffusion layer is not necessary as in the case of the conventional example, and the impurity profile after the heat treatment is slightly shifted from the state after implantation as shown in the figure. Thereafter, a contact hole is formed by a conventional method, and a wiring (not shown) is formed by applying an aluminum film and patterning the aluminum film, thereby completing the manufacturing process of this embodiment.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIGS. FIG.
(A)-(c), FIGS. 4 (a) and (b) show the second embodiment of the present invention.
FIG. 6 is a cross-sectional view in the order of steps for explaining the example. First,
An n-well 202 and a p-well 2 on a p-type semiconductor substrate 201
Then, a field oxide film 204 is formed by a selective oxidation method. Subsequently, a gate oxide film 205 is formed by thermal oxidation, and a gate electrode 207 is formed by deposition of polysilicon and patterning thereof.

Next, a film thickness of 10 to 2 is formed on the entire surface by thermal oxidation.
A silicon oxide film 215 having a thickness of 0 nm is formed.
The silicon nitride film 216 is formed to a thickness of 0.1 to 0.2 μm by the VD method.
m (FIG. 3A). Next, FIG.
As shown in (b), after covering the n-well 202 with a photoresist film 209, an n-type impurity, for example, arsenic is
Acceleration energy: 250 to 300 k sufficient to transmit silicon oxide film 215 and silicon nitride film 216
eV, dose: about 1.0 to 5.0 × 10 ¹⁵ cm ⁻² , and an n ⁺ -type diffusion layer 210 is formed in the source / drain formation region of the n-channel transistor in the p-well 203.

After removing the photoresist film 209, as shown in FIG. 3C, the silicon nitride film 21 is
6 is removed. At this time, the silicon oxide film 215 serves as a stopper for preventing the gate electrode 207 from being etched by phosphoric acid or the like. Then, an n-type impurity, for example, phosphorus is introduced over the entire surface under the conditions of an acceleration energy of 50 to 100 keV and a dose of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁴ cm ⁻² , and a p-channel transistor and an n-channel transistor are introduced. The n ⁻ -type diffusion layer 211 is formed in the source / drain formation region of FIG.

Next, as shown in FIG. 4A, the p-well 203 is coated with a photoresist film 212 by applying a photolithography technique, and this and the previously formed gate electrode 207 are used as a mask. , A p-type impurity, for example, boron fluoride, is introduced under the conditions of an acceleration energy of about 70 to 100 keV and a dose of about 1.0 to 5.0 × 10 ¹⁵ cm ^−2, so that the source / drain region of the p-channel transistor is A p ⁺ -type diffusion layer 213 is formed. Thus, a p-channel transistor that does not have an offset structure can be formed.

After removing the photoresist film 212, as shown in FIG. 4B, an interlayer insulating film 214 made of BPSG or the like is formed by a CVD method, and a heat treatment for reflow is performed. As a result, the activation of the previously implanted impurities is also performed at the same time. Then, by the usual method,
After the opening of the contact hole and the aluminum wiring process, the manufacturing process of this embodiment is completed.

[0023]

As described above, the MO according to the present invention is
A method of manufacturing an S-type semiconductor device includes forming a high-concentration source / drain region of an n-channel transistor through a mask-forming material layer, removing the mask-forming material layer, and then introducing an n-type impurity into the entire surface of the n-channel transistor. Forming a low-concentration source / drain region, and forming a high-concentration source / drain region of a p-channel transistor by introducing a p-impurity using a gate electrode as a mask. Source·
A semiconductor device having a p-channel transistor having a structure without offset and an n-channel transistor having an LDD structure can be manufactured without performing a heat treatment for indenting the drain region. Therefore, according to the present invention, p ⁺ which is the source / drain region of the p-channel transistor
Since the p-type diffusion layer is not unnecessarily deep and widely diffused, the p-channel transistor has good device isolation characteristics.
An OS-type semiconductor device can be provided.

[Brief description of the drawings]

FIG. 1 is a part of a process order cross-sectional view for explaining a manufacturing method according to a first embodiment of the present invention.

FIG. 2 is a sectional view in order of process in a step that follows the step of FIG. 1 for explaining the manufacturing method according to the first embodiment of the present invention.

FIG. 3 is a part of a process order cross-sectional view for explaining a manufacturing method according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing method according to a second embodiment of the present invention in the order of steps following the step of FIG. 3;

FIG. 5 is a part of a step-by-step cross-sectional view illustrating a manufacturing method of a conventional example.

FIG. 6 is a step-by-step cross-sectional view in a step that follows the step of FIG. 5 for explaining the manufacturing method of the conventional example.

[Explanation of symbols]

101, 201, 301 p-type semiconductor substrate 102, 202, 302 n-well 103, 203, 303 p-well 104, 204, 304 field oxide film 105, 205, 305 gate oxide film 106, 306 polysilicon film 107, 207, 307 Gate electrode 108, 308 Silicon oxide film 308a Side wall 109, 112, 209, 212, 309, 312 Photoresist film 110, 210, 310 n ⁺ type diffusion layer 111, 211, 311 n ⁻ type diffusion layer 113, 213, 313 p ⁺ type diffusion layers 114 and 214 interlayer insulating film 215 silicon oxide film 216 silicon nitride film

Claims (4)

(57) [Claims] (1) A gate electrode is formed on a first active region made of a p-type semiconductor and a second active region made of an n-type semiconductor on a semiconductor substrate via a gate insulating film. (2) including a side surface of the gate electrode with the mask forming material layer
A step of depositing over the entire surface of the semiconductor substrate, (3) a step of covering the second active region on the first mask member, (4) the first mask member, said gate electrode and said
An n-type impurity is ion-implanted using the mask forming material layer attached to the side surface of the gate electrode as a mask, and a high impurity concentration source / drain region is formed in a surface region of the first active region separated from the gate electrode. (5) removing the first mask body and the mask forming material layer; and (6) introducing an n-type impurity using the gate electrode as a mask and adjoining the gate electrode. Forming a low impurity concentration n-type diffusion layer in a surface region of the first and second active regions; (7) covering the first active region with a second mask body; 8) Using the second mask body and the gate electrode as a mask, p-type impurities are added to the n-type diffusion layer having a low impurity concentration.
And a source region having a high impurity concentration in a surface region of the second active region adjacent to the gate electrode.
Forming a drain region. A method for manufacturing a MOS type semiconductor device, comprising: 2. An etching protection method comprising a material having a different etching property from that of the mask forming material layer on at least the gate electrode between the steps (1) and (2). 2. The method according to claim 1, wherein a step of forming a layer is inserted. 3. The method according to claim 2, wherein said etching protection layer is formed by thermal oxidation. 4. The method according to claim 1, wherein the mask forming material layer formed in the step (2) is a silicon oxide film or a silicon nitride film containing impurities. Method.