JPH05102471A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05102471A JPH05102471A JP3256747A JP25674791A JPH05102471A JP H05102471 A JPH05102471 A JP H05102471A JP 3256747 A JP3256747 A JP 3256747A JP 25674791 A JP25674791 A JP 25674791A JP H05102471 A JPH05102471 A JP H05102471A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- interlayer insulating
- gate electrode
- channel region
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 14
- 239000001257 hydrogen Substances 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- -1 hydrogen ions Chemical class 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 7
- 238000005245 sintering Methods 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 description 7
- 238000002513 implantation Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Plasma & Fusion (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、この発明は半導体装
置の製造方法に関し、より詳しくは、電極配線工程後に
イオン注入を行ってチャネル領域のしきい値電圧を設定
する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of setting a threshold voltage of a channel region by performing ion implantation after an electrode wiring process.
【０００２】[0002]
【従来の技術】一般に、ＭＯＳトランジスタを製造する
場合、まず、ゲート酸化膜形成前に低エネルギ(５０kev
以下)でイオン注入を行うか、またはゲート酸化膜形成
後に中エネルギ(１８０kev程度)でイオン注入を行っ
て、チャネル領域(シリコン基板表面)の不純物濃度を設
定する。続いて、高温(９５０℃程度)でアニールを行っ
て、注入したイオンを活性化するとともに基板の結晶性
を回復させ、この後、電極配線を行う。しかしながら、
この方法ではイオン注入を行った後に電極配線工程を経
るため、ユーザの要望によってしきい値電圧を様々に設
定する場合、しきい値電圧を設定してから出荷できるま
での期間(以下「納期」という。)が長くなる(約８日間を
要する)という問題があった。2. Description of the Related Art Generally, when manufacturing a MOS transistor, first, a low energy (50 kev) is formed before forming a gate oxide film.
Ion implantation is performed in the following), or ion implantation is performed at medium energy (about 180 kev) after the gate oxide film is formed to set the impurity concentration in the channel region (silicon substrate surface). Subsequently, annealing is performed at a high temperature (about 950 ° C.) to activate the implanted ions and restore the crystallinity of the substrate, and thereafter, electrode wiring is performed. However,
With this method, the electrode wiring process is performed after ion implantation, so if the threshold voltage is set variously according to the user's request, the period from setting the threshold voltage to the time when the product can be shipped (hereinafter referred to as "delivery date") There is a problem that it becomes long (it takes about 8 days).
【０００３】そこで、最近になって、図３に示すよう
に、電極配線工程後にイオン注入を行ってチャネル領域
８のしきい値電圧を設定する方法が提案された。すなわ
ち、まず公知の手順により、シリコン基板１上に局所酸
化膜２と、ソースドレイン領域３a,３bと、ゲート酸化
膜７と、ゲート電極４と、層間絶縁膜５と、図示しない
電極配線を順に形成する。この上に、レジスト６を塗布
し、フォトリソグラフィを行って上記ゲート電極４上の
層間絶縁膜５を露出させる。この後、高エネルギ(３０
０〜７００kev)でイオン注入を行って、ゲート電極４直
下のチャネル領域８に硼素イオン(Ｂ+),燐イオン(Ｐ+)
などを導入し、続いて、低温(５００℃以下)でアニール
を行う。高エネルギ注入としているのは層間絶縁膜５を
通してチャネル領域８にイオンを到達させるためであ
り、低温アニールとしているのは電極配線の融点の制約
があるからである。この方法(以下「高エネルギ注入法」
という。)によれば、納期を３〜５日間に短縮すること
ができる。Therefore, recently, as shown in FIG. 3, a method has been proposed in which ion implantation is performed after the electrode wiring step to set the threshold voltage of the channel region 8. That is, first, the local oxide film 2, the source / drain regions 3a and 3b, the gate oxide film 7, the gate electrode 4, the interlayer insulating film 5, and the electrode wiring (not shown) are sequentially formed on the silicon substrate 1 by a known procedure. Form. A resist 6 is applied on this, and photolithography is performed to expose the interlayer insulating film 5 on the gate electrode 4. After this, high energy (30
Ion implantation is performed at 0 to 700 kev) to form boron ions (B + ) and phosphorus ions (P + ) in the channel region 8 directly below the gate electrode 4.
Etc. are introduced, and then annealing is performed at a low temperature (500 ° C. or lower). The high-energy implantation is for allowing the ions to reach the channel region 8 through the interlayer insulating film 5, and the low-temperature annealing is because the melting point of the electrode wiring is restricted. This method (hereinafter "high energy injection method")
Say. According to (), the delivery time can be shortened to 3 to 5 days.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記従
来の高エネルギ注入法では、質量が大きいＢ+,Ｐ+を高
エネルギで注入しているため、基板１の結晶性をアニー
ル(低温)によって完全には回復することができない。こ
のため、ＭＯＳトランジスタのスタンバイリーク電流が
増大するという問題がある。However, in the above-mentioned conventional high-energy implantation method, since B + and P + having a large mass are implanted with high energy, the crystallinity of the substrate 1 is completely annealed (at low temperature). Can't recover. Therefore, there is a problem that the standby leak current of the MOS transistor increases.
【０００５】そこで、この発明の目的は、納期を短縮で
きる上、基板の結晶性を完全に回復してＭＯＳトランジ
スタのスタンバイリーク電流を低減できる半導体装置の
製造方法を提供することにある。Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device which can shorten the delivery time and can completely recover the crystallinity of the substrate to reduce the standby leak current of the MOS transistor.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するた
め、この発明の半導体装置の製造方法は、シリコン基板
上にゲート絶縁膜、ゲート電極、層間絶縁膜および電極
配線を順に形成した後、上記層間絶縁膜を通して上記ゲ
ート電極の直下のチャネル領域に水素イオンを注入し、
続いて、水素雰囲気中で熱処理を行うことを特徴として
いる。In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of forming a gate insulating film, a gate electrode, an interlayer insulating film and an electrode wiring in order on a silicon substrate, Hydrogen ions are implanted into the channel region directly below the gate electrode through the interlayer insulating film,
Subsequently, heat treatment is performed in a hydrogen atmosphere.
【０００７】[0007]
【作用】既に知られているように、シリコン基板中に存
在する水素は硼素のキャリア濃度を低下させる(Ｓ.Ｊ.
ペアトン(Ｐearton)ら;マテリアルズ・サイエンス・フ
ォーラム Ｖol.３８〜４１p２５〜３８)。したがっ
て、水素をチャネル領域にイオン注入することによっ
て、チャネル領域のしきい値電圧を設定することができ
る。ここで、水素イオン(Ｈ+)は、極めて小さく軽いと
いう性質を有している。実際に、Ｂ+,Ｐ+に比して原子
半径でそれぞれ１／３.３,１／３.７、質量比でそれぞ
れ１／１１,１／３１となっている。したがって、電極
配線工程後であっても比較的低い注入エネルギ(１６０k
ev以下)でもってチャネル領域に到達させることがで
き、注入によって基板に与えるダメージを従来に比して
低減することができる。この結果、水素雰囲気中での通
常の熱処理(いわゆるＨ2シンター)を行うことにより、
５００℃以下の低温でもって基板の結晶性が完全に回復
され、ＭＯＳトランジスタのスタンバイリーク電流が低
減される。また、電極配線工程後にしきい値電圧を設定
しているので、従来の高エネルギ注入法と同様に納期が
３〜５日間に短縮される。As already known, hydrogen existing in the silicon substrate lowers the carrier concentration of boron (SJ.
Pearton et al .; Materials Science Forum Vol.38-41p25-38). Therefore, the threshold voltage of the channel region can be set by ion-implanting hydrogen into the channel region. Here, the hydrogen ion (H + ) has the property of being extremely small and light. Actually, the atomic radii are 1 / 3.3 and 1 / 3.7, and the mass ratios are 1/11 and 1/31, respectively, as compared with B + and P + . Therefore, even after the electrode wiring process, relatively low implantation energy (160 k
It is possible to reach the channel region with (e.g. ev or less), and the damage given to the substrate by implantation can be reduced as compared with the conventional case. As a result, by performing a normal heat treatment (so-called H 2 sintering) in a hydrogen atmosphere,
The crystallinity of the substrate is completely restored at a low temperature of 500 ° C. or lower, and the standby leak current of the MOS transistor is reduced. Further, since the threshold voltage is set after the electrode wiring process, the delivery time can be shortened to 3 to 5 days as in the conventional high energy injection method.
【０００８】[0008]
【実施例】以下、この発明の半導体装置の製造方法を実
施例により詳細に説明する。The method for manufacturing a semiconductor device of the present invention will be described in detail below with reference to embodiments.
【０００９】まず、図１に示すように、公知の手順によ
り、シリコン基板１上に局所酸化膜２と、ソースドレイ
ン領域３a,３bと、ゲート酸化膜７と、ゲート電極４
と、層間絶縁膜５と、図示しない電極配線を順に形成す
る。上記ゲート酸化膜７の膜厚は２０nmとし、ゲート電
極４はＷＳiとポリシリコンとの２層構造(膜厚２００nm
／１５０nm)とする。また、層間絶縁膜５はＢＰＳＧ(ボ
ロン・リン・シリケート・ガラス)とＮＳＧ(ノンドープ
・シリケート・ガラス)との２層構造(合計膜厚６００n
m)とする。この上に、レジスト６を塗布し、フォトリソ
グラフィを行って上記ゲート電極４上の層間絶縁膜５を
露出させる。この後、低エネルギ(８５kev)でイオン注
入を行って、ゲート電極４直下のチャネル領域８に水素
イオン(Ｈ+)を導入する。ここで、図２に示すように、
注入エネルギは層間絶縁膜５の膜厚に応じて基板表面に
到達するように調整している。また、ドーズ量は３×１
０14cm-2とする。これにより、チャネル領域８のしきい
値電圧を設定する。続いて、低温(５００℃),水素雰囲
気中で通常の熱処理(いわゆるＨ2シンター)を行う。こ
れにより、基板１の結晶性を完全に回復することがで
き、ＭＯＳトランジスタのスタンバイリーク電流を低減
することができる。また、電極配線形成後にしきい値電
圧を設定しているので、従来の高エネルギ注入法と同様
に納期を３〜５日間に短縮することができる。First, as shown in FIG. 1, a local oxide film 2, source / drain regions 3a and 3b, a gate oxide film 7, and a gate electrode 4 are formed on a silicon substrate 1 by a known procedure.
Then, the interlayer insulating film 5 and the electrode wiring (not shown) are sequentially formed. The gate oxide film 7 has a film thickness of 20 nm, and the gate electrode 4 has a two-layer structure of WSi and polysilicon (film thickness 200 nm).
/ 150 nm). The interlayer insulating film 5 has a two-layer structure of BPSG (boron phosphorus silicate glass) and NSG (non-doped silicate glass) (total film thickness 600 n).
m). A resist 6 is applied on this, and photolithography is performed to expose the interlayer insulating film 5 on the gate electrode 4. After that, ion implantation is performed at low energy (85 kev) to introduce hydrogen ions (H + ) into the channel region 8 directly below the gate electrode 4. Here, as shown in FIG.
The implantation energy is adjusted so as to reach the substrate surface according to the film thickness of the interlayer insulating film 5. Also, the dose amount is 3 × 1
0 14 cm -2 . Thereby, the threshold voltage of the channel region 8 is set. Then, ordinary heat treatment (so-called H 2 sintering) is performed in a hydrogen atmosphere at a low temperature (500 ° C.). As a result, the crystallinity of the substrate 1 can be completely restored, and the standby leak current of the MOS transistor can be reduced. Further, since the threshold voltage is set after the electrode wiring is formed, the delivery time can be shortened to 3 to 5 days as in the conventional high energy injection method.
【００１０】[0010]
【発明の効果】以上より明らかなように、この発明の半
導体装置の製造方法は、シリコン基板上にゲート絶縁
膜、ゲート電極、層間絶縁膜および電極配線を順に形成
した後、上記層間絶縁膜を通して上記ゲート電極の直下
のチャネル領域に水素イオンを注入し、続いて、水素雰
囲気中で熱処理を行うので、従来の高エネルギ注入法と
同様に納期を短縮することができる。しかも、水素イオ
ンを低エネルギでチャネル領域に到達させることがで
き、基板に与えるダメージを従来に比して低減すること
ができる。したがって、通常のＨ2シンターを行なうこ
とにより、基板の結晶性を完全に回復でき、ＭＯＳトラ
ンジスタのスタンバイリーク電流を低減することができ
る。As is apparent from the above, according to the method of manufacturing a semiconductor device of the present invention, a gate insulating film, a gate electrode, an interlayer insulating film and an electrode wiring are sequentially formed on a silicon substrate, and then the interlayer insulating film is formed. Since hydrogen ions are implanted into the channel region immediately below the gate electrode and then heat treatment is performed in a hydrogen atmosphere, the delivery time can be shortened as in the conventional high energy implantation method. Moreover, hydrogen ions can reach the channel region with low energy, and damage to the substrate can be reduced as compared with the conventional case. Therefore, by performing normal H 2 sintering, the crystallinity of the substrate can be completely restored, and the standby leak current of the MOS transistor can be reduced.
【図１】 この発明の一実施例の半導体装置の製造方法
を説明する図である。FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】 層間絶縁膜の膜厚と注入すべき水素イオンの
エネルギとの関係を示すである。FIG. 2 is a graph showing the relationship between the film thickness of an interlayer insulating film and the energy of hydrogen ions to be implanted.
【図３】 従来の高エネルギ注入法を説明する図であ
る。FIG. 3 is a diagram illustrating a conventional high energy injection method.
１ シリコン基板 ２ 局所酸化膜 ３ ソースドレイン領域 ４ ゲート電極 ５ 層間絶縁膜 ６ レジスト ７ ゲート絶縁膜 ８ チャネル領域 1 Silicon Substrate 2 Local Oxide Film 3 Source / Drain Region 4 Gate Electrode 5 Interlayer Insulation Film 6 Resist 7 Gate Insulation Film 8 Channel Region
Claims (1)
電極、層間絶縁膜および電極配線を順に形成した後、 上記層間絶縁膜を通して上記ゲート電極の直下のチャネ
ル領域に水素イオンを注入し、 続いて、水素雰囲気中で熱処理を行うことを特徴とする
半導体装置の製造方法。1. A gate insulating film, a gate electrode, an interlayer insulating film, and an electrode wiring are sequentially formed on a silicon substrate, and then hydrogen ions are implanted into the channel region directly below the gate electrode through the interlayer insulating film. A method for manufacturing a semiconductor device, which comprises performing heat treatment in a hydrogen atmosphere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3256747A JPH05102471A (en) | 1991-10-03 | 1991-10-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3256747A JPH05102471A (en) | 1991-10-03 | 1991-10-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05102471A true JPH05102471A (en) | 1993-04-23 |
Family
ID=17296885
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3256747A Pending JPH05102471A (en) | 1991-10-03 | 1991-10-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05102471A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0884773A2 (en) * | 1997-06-09 | 1998-12-16 | Nec Corporation | Method of making an MIS transistor |
| US6274439B1 (en) | 1997-02-06 | 2001-08-14 | Nec Corporation | Process for fabricating semiconductor device with field effect transistor changeable in threshold voltage with hydrogen ion after formation of wirings |
| KR100760344B1 (en) * | 2006-03-24 | 2007-09-20 | 한국원자력연구원 | Method for manufacturing semiconductor devices |
| WO2024040698A1 (en) * | 2022-08-25 | 2024-02-29 | 长鑫存储技术有限公司 | Semiconductor structure manufacturing method and semiconductor structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55162240A (en) * | 1979-06-04 | 1980-12-17 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and its manufacture |
| JPS6084866A (en) * | 1983-10-14 | 1985-05-14 | Seiko Epson Corp | Read only memory |
| JPH042163A (en) * | 1990-04-18 | 1992-01-07 | Oki Electric Ind Co Ltd | Manufacture of mask rom |
-
1991
- 1991-10-03 JP JP3256747A patent/JPH05102471A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55162240A (en) * | 1979-06-04 | 1980-12-17 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and its manufacture |
| JPS6084866A (en) * | 1983-10-14 | 1985-05-14 | Seiko Epson Corp | Read only memory |
| JPH042163A (en) * | 1990-04-18 | 1992-01-07 | Oki Electric Ind Co Ltd | Manufacture of mask rom |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6274439B1 (en) | 1997-02-06 | 2001-08-14 | Nec Corporation | Process for fabricating semiconductor device with field effect transistor changeable in threshold voltage with hydrogen ion after formation of wirings |
| EP0884773A2 (en) * | 1997-06-09 | 1998-12-16 | Nec Corporation | Method of making an MIS transistor |
| EP0884773A3 (en) * | 1997-06-09 | 2000-01-12 | Nec Corporation | Method of making an MIS transistor |
| US6162710A (en) * | 1997-06-09 | 2000-12-19 | Nec Corporation | Method for making MIS transistor |
| KR100285995B1 (en) * | 1997-06-09 | 2001-04-16 | 가네꼬 히사시 | Manufacturing method of MIS transistor |
| KR100760344B1 (en) * | 2006-03-24 | 2007-09-20 | 한국원자력연구원 | Method for manufacturing semiconductor devices |
| WO2024040698A1 (en) * | 2022-08-25 | 2024-02-29 | 长鑫存储技术有限公司 | Semiconductor structure manufacturing method and semiconductor structure |
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