KR100760344B1 - Method for manufacturing semiconductor devices - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to improve characteristics of a gate oxide layer of a MOS device and to enhance operation characteristics of the MOS device by preventing the degradation of the gate oxide layer using an ion implantation capable of distributing minimally hydrogen or heavy hydrogen ions in the gate oxide layer and distributing maximally the hydrogen or heavy hydrogen ions at an interface between the gate oxide layer and a silicon substrate. A gate oxide layer(11) is formed on a silicon substrate(10). A gate electrode is formed on the gate oxide layer. Source/drain regions spaced apart from each other are formed in the substrate. A metal line electrode is formed at the resultant structure to connect electrically the gate electrode and the source/drain regions with each other. An ion implantation is performed on the resultant structure to prevent the degradation of the gate oxide layer. At this time, the distribution of ions is maximal at an interface between the gate oxide layer and the substrate and minimal in the gate oxide layer. Hydrogen ions or heavy hydrogen ions are used for the ion implantation. The ion implantation is performed at the energy of 30 to 100 KeV and in the ion irradiation amount range of 1E12 to 1E14/cm^2.

Description

Method of manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES}

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional structural view showing the main parts of a general metal oxide semiconductor (MOS) field-effect transistor (FET) to which a method of manufacturing a semiconductor device according to the present invention is applied.

FIG. 2 is an exemplary view showing a defect occurring in the gate oxide film of FIG. 1. FIG.

3 is an exemplary view illustrating a defect generated at an interface between a silicon substrate and a gate oxide film of FIG. 1.

Figure 4 is a graph showing the concentration distribution of ions implanted by conventional hydrogen or deuterium heat treatment.

5A to 5H are flowcharts showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

6A to 6I are process flowcharts illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

Fig. 7 is a graph showing the ion distribution of hydrogen or deuterium at the interface between the silicon substrate and the gate oxide film according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to increasing the ion distribution of hydrogen or deuterium at the interface between a silicon substrate and the gate oxide film, and to reducing the ion distribution of hydrogen or deuterium in the gate oxide film. The manufacturing method of the semiconductor element made to improve the characteristic is related.

In general, a metal oxide semiconductor (MOS) device, for example, a MOS capacitor, a field-effect transistor (FET), and the like includes a thin insulating film called a gate oxide film. Since the physical properties of the gate oxide, which is one of the factors that determine the electrical characteristics and reliability of the MOS device, are very important, many studies have been conducted.

In the typical MOS field effect transistor as shown in FIG. 1, an inversion region, that is, a channel region, is applied to the silicon substrate 10 under the gate oxide film 11 by a gate voltage applied to the gate electrode 13. By this induction, a current may flow between the source / drain regions S / D through the inversion region. If the gate oxide film 11 does not have sufficient insulating characteristics, a portion of the current flowing through the inversion region also flows to the gate electrode 13, thereby reducing the current flowing through the source / drain region S / D. . The reason why the gate oxide film 11 does not have sufficient insulating characteristics is that defects exist in the gate oxide film 11. Currently, an amorphous silicon oxide film is mainly used as the gate oxide film 11.

Defects in the gate oxide film 11 are generally caused by breakage of the chemical bonds of the gate oxide film 11 when the gate oxide film 11 is subjected to electrical stress for a long time. If electrons or holes are trapped in these defects, the defects may be negatively charged or positively charged, thereby deteriorating an insulating property of the gate oxide film 11. There are various kinds of chemical bond breakages that may occur in the gate oxide layer 11 as illustrated in FIGS. 2 and 3.

When the gate oxide layer 11 is formed of, for example, SiO ₂ material, as shown in FIG. 2, nonbridging oxygen, vacancy, hydrogen, and the like, are formed in the gate oxide layer 11. Major defects such as hydrogen bond ions (H + or OH radicals) may occur. The unbound oxygen serves as a neutral electron-trap center, the baconcies function as a positively charged center, and hydrogen and hydrogen bond ions (H + or OH radicals) It diffuses into the gate oxide and serves as a main cause of breaking the chemical bond of the gate oxide.

In addition, a defect such as a dangling bond, which is an unbonded bond, may occur at the interface between the silicon substrate 10 and the gate oxide film 11. Due to the lattice constant difference between the crystalline silicon (Si) and the amorphous silicon oxide film (SiO ₂ ), there are silicon atoms which are not chemically bonded, which acts as an interface trap.

Currently, in order to reduce the dangling bond density between the silicon substrate and the silicon oxide film, a method of passivation with hydrogen ions through heat treatment with an atmosphere such as hydrogen is used. The method is used as a basic semiconductor manufacturing process, and the interface trap is combined with hydrogen ions by passivation at a temperature of about 400 to 500 ° C. and hydrogen and nitrogen atmosphere conditions in the final step after fabrication of the device.

However, according to this method, the hydrogen concentration is distributed as shown in FIG. 4 over the entire silicon oxide film. As mentioned above, the hydrogen ions present at the Si / SiO ₂ interface serve to remove dangling bonds, but the hydrogen ions present inside the SiO ₂ film provide a cause for generating oxygen traps.

In order to make up for the disadvantages and disadvantages of the hydrogen ions, a method of injecting deuterium ions into the SiO ₂ membrane instead of the hydrogen ions has been proposed. In this method, the deuterium ions at the Si / SiO ₂ interface can effectively suppress the degradation of the SiO ₂ film by heat-treating the MoS element in an atmospheric pressure or deuterium atmosphere, but the deuterium ions present in a large amount in the SiO ₂ film Still degraded the SiO ₂ film.

Therefore, in order to obtain a highly reliable Mohs device, a chemical structure in which no hydrogen (or deuterium) ions are present in the SiO ₂ film but concentrated hydrogen (and deuterium) ions at the Si / SiO ₂ interface is recognized as an ideal structure. have. Therefore, if the concentration difference of hydrogen or deuterium ions can be realized according to the depth of the gate oxide film of the MOS device, the reliability of the MOS device can be improved. However, this attempt is not carried out at all in the present semiconductor manufacturing basic process.

Accordingly, an object of the present invention is to improve the electrical characteristics and reliability of the MOS device by increasing the concentration distribution of hydrogen or deuterium ions at the interface between the silicon substrate and the gate oxide film while reducing the concentration distribution of hydrogen or deuterium ions in the gate oxide film. To do that.

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In order to achieve the above object, a method of manufacturing a semiconductor device according to an embodiment of the present invention, forming a gate oxide film on a silicon substrate; Forming a gate electrode on the gate oxide film; Forming a source / drain region in the silicon substrate so as to be spaced apart from the gate electrode; Forming a wiring electrode electrically connected to the gate electrode and a source / drain region; And ion implanting the ions into the gate oxide film so as to maximize the distribution of ions to prevent deterioration of the gate oxide film at an interface between the gate oxide film and the silicon substrate and to lower the distribution of the ions in the gate oxide film. Including,
Ion implantation of any one of hydrogen ions and deuterium ions as the ions.

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Preferably, the ion may be ion implanted at an energy of 30 to 100 KeV and an ion irradiation amount of 1E12 to 1E14 / cm ² .

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional structural view showing the main part of a general MOS field effect transistor of the method for manufacturing a semiconductor device of the present invention, Figures 5a to 5h is a process flowchart showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. .

Referring to FIG. 1, in the MOS field effect transistor, a gate oxide film 11 is disposed on a portion of the silicon substrate 10, a gate electrode 13 is disposed on the gate oxide film 11, and the gate electrode 13 is disposed. The nitride film spacer 17 is disposed on the side surface of the silicon substrate 10, the interlayer insulating film 19 is laminated on the silicon substrate 10, the gate electrode 13, and the nitride film spacer 17, and the source / drain A wiring electrode 21 is disposed in each contact hole (or via hole) of the interlayer insulating layer 19 so as to be electrically connected to the region S / D and the gate electrode 13, respectively, with the gate electrode 13 at the center. The source / drain regions S / D are spaced apart from each other and are disposed in the silicon substrate 10.

Here, the gate oxide film 11 may be formed of an oxide film, for example, a SiO ₂ film or an HfO ₂ film, and preferably has a suitable thickness in consideration of operating characteristics of a MOS field effect transistor to be manufactured. The gate electrode 13 may be composed of a polycrystalline silicon film, preferably a high concentration polycrystalline silicon film, and a low resistance metal layer (not shown) on the polycrystalline silicon film to lower the resistance of the gate electrode 13. This may be further configured. Although the interlayer insulating film 19 is illustrated as being composed of one layer for convenience, it may actually be composed of a plurality of layers of various materials. In addition, although the wiring electrode 21 is illustrated as being composed of one layer for convenience, a barrier metal film is interposed between the gate electrode 13 or the source / drain region S / D and the wiring electrode 21. Can be.

Although not shown in the drawings, in the case of a MOS device such as a MOS capacitor, the electrode such as the gate electrode may be formed of a metal film such as an aluminum (Al) film or a polysilicon film of high concentration.

Hereinafter, a method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described in detail with reference to FIGS. 5A to 5H. The same code | symbol is attached | subjected to the part which has the same structure and the same effect | action as the part of FIG.

Referring to FIG. 5A, first, a gate oxide film 11 is grown on a front surface of a substrate, for example, a silicon substrate 10. In this case, the gate oxide film 11 may be formed of a SiO ₂ film or an HfO ₂ film by a conventional thermal oxidation process. The thickness of the gate oxide film 11 may be appropriately determined in consideration of operating characteristics of the MOS field effect transistor, and the like. In the case of the MOS field effect transistor, the gate oxide film is grown to a thickness of about 3 to 20 nm, In this case, it is preferable to grow the gate oxide film to a thickness of about 15 to 25 nm.

Referring to FIG. 5B, a pattern of an ion implantation mask is formed on the gate oxide film 11, for example, the photoresist pattern PR1 in which a window is positioned on the gate formation region of the gate oxide film 11 using a photolithography process. Form.

Thereafter, hydrogen ions (H +) or deuterium ions (D +) are implanted into the exposed gate oxide film 11 in the window of the photoresist pattern PR1 using the ion implantation process.

In this case, as shown in FIG. 7, the ion implantation energy is low energy, for example, 30 to 100 KeV so that the maximum value of the ion implantation concentration may appear at the interface between the silicon substrate 10 and the gate oxide layer 11. The ion implantation amount is preferably in the range of 1E12 to 4E14 / cm 2.

Therefore, the maximum ion implantation concentration (x) at the ion implantation depth x in the gate oxide film 11, which is a SiO ₂ film, for example, at a third depth x3 corresponding to the interface between the silicon substrate 10 and the gate oxide film 11. When the value appears, deterioration of the gate oxide film 11, which is an SiO ₂ film, can be effectively suppressed because hydrogen ions (H +) or deuterium ions (D +) present in a large amount at the Si / SiO ₂ interface serve to remove the dangling bond. Can be. Furthermore, since hydrogen ions (H +) or deuterium ions (D +) are distributed less at the first and second depths (x1, x2) in the gate oxide film 11, the overlap in the gate oxide film 11 is less than in the prior art. The deterioration of the gate oxide film 11 generated and furthermore can be effectively suppressed.

Meanwhile, in order to activate the ion implanted hydrogen ions (H +) or deuterium ions (D +), it is preferable to perform a subsequent heat treatment process in an inert atmosphere.

Referring to FIG. 5C, after removing the photoresist pattern PR1 of FIG. 5B, a conductive film, for example, a polysilicon film, for the gate electrode 13 is formed on the gate oxide film 11 using chemical vapor deposition or the like. Laminated.

At this time, in order to dope the polycrystalline silicon film at a high concentration, during the lamination of the polycrystalline silicon film, the polycrystalline silicon film is doped with an impurity of a desired conductivity type, or after the lamination of the polycrystalline silicon film is completed, the impurity of a desired conductivity type is formed in the polycrystalline silicon film. Can be implanted at high concentrations.

Further, in order to lower the resistance of the polysilicon film, it is also possible to further form a low resistance metal film, that is, a silicide film (not shown), on the polycrystalline silicon film.

Thereafter, an etch mask pattern, for example, a photoresist pattern PR2, is formed on a portion of the polysilicon film, for example, a gate electrode formation region, to form a gate electrode.

Next, the gate electrode 13 and the gate oxide film 11 outside the photoresist pattern PR2 are removed to form the gate electrode 13 and the gate oxide film 11 on the gate electrode formation region of the silicon substrate 10. Form a pattern.

Although not shown in the drawings, in the case of a MOS device such as a MOS capacitor, the electrode such as the gate electrode may be formed of a metal film such as an aluminum (Al) film or a polysilicon film of high concentration.

Referring to FIG. 5D, a lightly doped drain (LDD) source / drain is formed on the surface of the silicon substrate 10 using the photoresist pattern PR2 of FIG. 5C as an ion implantation mask using an ion implantation process. Ion implantation of impurities for the region at low concentration.

Here, when the silicon substrate 10 is of the first conductivity type, for example, p-type, the LED source / drain region is ion-implanted at low concentration with an n-type impurity, for example, the second conductivity type, and conversely, If the silicon substrate 10 is of a first conductivity type, for example n-type, the LED source / drain region is ion-implanted at low concentration with an impurity of p-type, for example, the second conductivity type.

Referring to FIG. 5E, the photoresist pattern PR2 of FIG. 5D is removed to expose the gate electrode 13. Then, an insulating film, for example, a silicon oxide film 15 is laminated not only on the top and side surfaces of the gate electrode 13 but also on the surface of the silicon substrate 10 by chemical vapor deposition or the like, and the silicon oxide film An insulating film, for example, silicon nitride film 16 is deposited on (15).

Referring to FIG. 5F, the silicon oxide film 15 may be etched only on the side surface of the gate electrode 13 by etching the silicon nitride film 16 and the silicon oxide film 15 using an etch back process having anisotropic etching characteristics or the like. The nitride film spacer 17 is formed by leaving the silicon nitride film 16 therebetween. In this case, it is preferable that a part of the silicon oxide film 15 and the silicon nitride film 16 do not remain on the gate electrode 13 or the upper surface of the silicon substrate 10. This is because when a part of the silicon oxide film 15 and the silicon nitride film 16 remain on the gate electrode 13 or the upper surface of the silicon substrate 10, the gate electrode 13 or the source / drain region of FIG. This is because the electrical contact resistance between (S / D) and each corresponding wiring electrode 21 becomes high.

Referring to FIG. 5G, a source of high concentration on the silicon substrate 10 is then used using the gate electrode 13, the silicon oxide film 15, and the nitride film spacer 17 as an ion implantation mask using an ion implantation process. Ion implantation of impurities for the drain region is performed at high concentration.

Here, as shown in FIG. 5D, if the LED source / drain region is ion-implanted with n-type impurity, the high concentration source / drain region is ion-implanted with n-type impurity at high concentration, and conversely, the LED If the source / drain regions are ion-implanted with p-type impurities, the high concentration source / drain regions are ion-implanted with p-type impurities.

Subsequently, the source / drain regions S / D are formed by activating the ion implantation impurity using a heat treatment process.

Referring to FIG. 5H, an interlayer insulating film 19 is deposited on the silicon substrate 10, the gate electrode 13, and the nitride film spacer 17 by using chemical vapor deposition. Here, the interlayer insulating film 19 is illustrated as being composed of one layer for convenience, but may be actually composed of a plurality of layers in which several layers of different materials are stacked.

Next, the interlayer insulating film 19 is planarized using a planarization process, for example, a chemical mechanical polishing (CMP) process.

Then, a wiring electrode 21 for electrically connecting the source / drain region S / D and the contact region of the gate electrode 13 is formed using a metal wiring process. That is, contact holes (or via holes) for exposing, for example, the contact regions of the source / drain regions S / D and the gate electrode 13 are formed in some regions of the interlayer insulating layer 19, and A metal film is stacked in the contact hole (or via hole) and on the interlayer insulating film 19 to fill a contact hole (or via hole), and the metal film on the interlayer insulating film 19 is formed as a pattern of each wiring electrode 21. Form. In addition, a barrier metal film (not shown) is further laminated between the gate electrode 13 or the source / drain region S / D and the wiring electrode 21 before the deposition of the metal film for the wiring electrode 21. It is also possible. It is also possible to form a wiring electrode on the plug after forming a plug of the metal layer existing only in the contact hole (or via hole). Therefore, the manufacturing method of the semiconductor element by this invention is completed.

Hereinafter, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 6A to 6I.

6A to 6I are process flowcharts illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention. The same code | symbol is attached | subjected to the part which has the same structure and the same operation | movement as the part of FIGS. 5A-5H.

Referring to FIG. 6A, first, a gate oxide film 11 is grown on a front surface of a substrate, for example, a silicon substrate 10. In this case, the gate oxide film 11 may be formed of a SiO ₂ film or an HfO ₂ film by a conventional thermal oxidation process. The thickness of the gate oxide film 11 may be appropriately determined in consideration of operating characteristics of the MOS field effect transistor, and the like. In the case of the MOS field effect transistor, the gate oxide film is grown to a thickness of about 3 to 20 nm, In this case, it is preferable to grow the gate oxide film to a thickness of about 15 to 25 nm.

Referring to FIG. 6B, a conductive film for the gate electrode 13, for example, a polysilicon film, is laminated on the gate oxide film 11 using chemical vapor deposition or the like. For the high concentration doping of the polycrystalline silicon film, during the lamination of the polycrystalline silicon film, the polycrystalline silicon film is doped with a desired conductivity type impurity, or after laminating the polycrystalline silicon film and the desired concentration of the impurity of a desired conductivity type is formed in the polycrystalline silicon film. Ion implantation.

Further, in order to lower the resistance of the polysilicon film, it is also possible to further form a low resistance metal film, that is, a silicide film (not shown), on the polycrystalline silicon film.

Thereafter, an etch mask pattern, for example, a photoresist pattern PR2, is formed on a portion of the polysilicon film, for example, a gate electrode formation region, to form a gate electrode.

Next, the gate electrode 13 and the gate oxide film 11 outside the photoresist pattern PR2 are removed to form the gate electrode 13 and the gate oxide film 11 on the gate electrode formation region of the silicon substrate 10. Form a pattern.

Although not shown in the drawings, in the case of a MOS device such as a MOS capacitor, the electrode such as the gate electrode may be formed of a metal film such as an aluminum (Al) film or a polysilicon film of high concentration.

Referring to FIG. 6C, after the photoresist pattern PR2 of FIG. 6B is used as an ion implantation mask using an ion implantation process, impurities for an LED element / drain region are implanted at low concentration in the silicon substrate 10. do.

Here, when the silicon substrate 10 is of the first conductivity type, for example, p-type, the LED source / drain region is ion-implanted at low concentration with an n-type impurity, for example, the second conductivity type, and conversely, If the silicon substrate 10 is of a first conductivity type, for example n-type, the LED source / drain region is ion implanted at low concentration with a p-type impurity, for example, the second conductivity type.

Referring to FIG. 6D, the gate electrode 13 is exposed by removing the photoresist pattern PR2 of FIG. 6C. Then, an insulating film, for example, a silicon oxide film 15 is laminated not only on the top and side surfaces of the gate electrode 13 but also on the surface of the silicon substrate 10 by chemical vapor deposition or the like, and the silicon oxide film An insulating film, for example, silicon nitride film 16 is deposited on (15).

Referring to FIG. 6E, the silicon oxide film 15 may be etched only on the side surface of the gate electrode 13 by etching the silicon nitride film 16 and the silicon oxide film 15 by using an etch back process having anisotropic etching characteristics or the like. The nitride film spacer 17 is formed by leaving the silicon nitride film 16 therebetween. In this case, it is preferable that a part of the silicon oxide film 15 and the silicon nitride film 16 do not remain on the gate electrode 13 or the upper surface of the silicon substrate 10. This is because when a part of the silicon oxide film 15 and the silicon nitride film 16 remain on the gate electrode 13 or the upper surface of the silicon substrate 10, the gate electrode 13 or the source / drain region of FIG. This is because the electrical contact resistance between (S / D) and each corresponding wiring electrode 21 becomes high.

Referring to FIG. 6F, a source of high concentration on the silicon substrate 10 is then used using the gate electrode 13, the silicon oxide film 15, and the nitride film spacer 17 as an ion implantation mask using an ion implantation process. Ion implantation of impurities for the drain region is performed at high concentration.

6C, if the LED source / drain region is ion-implanted with n-type impurity, the source / drain region of high concentration is ion-implanted with n-type impurity, and conversely, the LED source is drained. If the / drain region is ion-implanted with p-type impurity, the high concentration source / drain region is ion-implanted with p-type impurity at high concentration.

Subsequently, the source / drain regions S / D are formed by activating the ion implantation impurity using a heat treatment process.

Referring to FIG. 6G, an interlayer insulating film 19 is deposited on the silicon substrate 10, the gate electrode 13, and the nitride film spacer 17 by using chemical vapor deposition. Here, the interlayer insulating film 19 is illustrated as being composed of one layer for convenience, but may be actually composed of a plurality of layers in which several layers of different materials are stacked.

Next, the interlayer insulating film 19 is planarized using a planarization process, for example, a chemical mechanical polishing (CMP) process.

Then, a wiring electrode 21 for electrically connecting the source / drain region S / D and the contact region of the gate electrode 13 is formed using a conventional metallization process. That is, contact holes (or via holes) for exposing, for example, the contact regions of the source / drain regions S / D and the gate electrode 13 are formed in some regions of the interlayer insulating layer 19, and A metal film is stacked in the contact hole (or via hole) and on the interlayer insulating film 19 to fill a contact hole (or via hole), and the metal film on the interlayer insulating film 19 is formed as a pattern of each wiring electrode 21. Form. In addition, a barrier metal film (not shown) is further laminated between the gate electrode 13 or the source / drain region S / D and the wiring electrode 21 before the deposition of the metal film for the wiring electrode 21. It is also possible. It is also possible to form a wiring electrode on the plug after forming a plug of the metal layer existing only in the contact hole (or via hole).

Referring to FIG. 6H, a pattern of an ion implantation mask is formed on a portion of the interlayer insulating layer 19, for example, a photoresist pattern in which a window is formed on a gate formation region of the gate oxide layer 11 using a photolithography process. PR3).

Thereafter, hydrogen ions (H +) or deuterium ions (D +) are implanted into the gate oxide film 11 positioned in the window of the photoresist pattern PR3 using the ion implantation process.

In this case, as shown in FIG. 7, the ion implantation energy is low energy, for example, 30 to 100 KeV so that the maximum value of the ion implantation concentration can be seen at the interface between the silicon substrate 10 and the gate oxide film 11. The ion implantation amount is preferably in the range of 1E12 to 4E14 / cm 2.

Therefore, when the ion implantation depth in the gate oxide film 11 that is the SiO ₂ film, for example, the maximum value of the ion implantation concentration appears at the third depth x3 corresponding to the interface between the silicon substrate 10 and the gate oxide film 11, In addition, since a large amount of hydrogen ions (H +) or deuterium ions (D +) present in the Si / SiO ₂ interface serves to remove the dangling bond, deterioration of the gate oxide film 11, which is a SiO ₂ film, can be effectively suppressed. Furthermore, since less hydrogen ions (H +) or deuterium ions (D +) are distributed in the first and second depths (x1, x2) in the gate oxide film 11, the oxygen traps in the gate oxide film 11 are less than in the prior art. It is less produced and furthermore, the deterioration of the gate oxide film 11 can be effectively suppressed.

Referring to FIG. 6I, the photoresist pattern PR3 of FIG. 6H is removed, and a heat treatment process is performed in an inert atmosphere to activate the ion implanted hydrogen ions (H +) or deuterium ions (D +). Therefore, the manufacturing method of the semiconductor element by this invention is completed.

On the other hand, for convenience of description of the present invention has been described with respect to the MOS field effect transistor, but may be applied to the dielectric film of the MOS capacitor, the same, and for convenience of explanation, description thereof will be omitted.

As described above, the method of manufacturing a semiconductor device according to the present invention uses the ion implantation process to minimize the distribution of hydrogen or deuterium ions in the gate oxide film, while maximally distributing hydrogen or deuterium ions at the interface between the gate oxide film and the silicon substrate. Deterioration of the gate oxide film can be prevented. Therefore, the present invention can improve the characteristics of the gate oxide film of the MOS element such as the MOS field effect transistor and the MOS capacitor, and further improve the operation characteristics of the MOS field effect transistor. In addition, the present invention can improve the reliability of the MOS field effect transistor. In other words, the lifetime of PMOS field effect transistors increases under negative-bias-temperature instability (NBTI) stress. Hot carrier stress increases the lifetime of both PMOS field effect transistors and NMOS field effect transistors. The breakdown life of the gate oxide film also increases.

On the other hand, the present invention has been described in connection with the above-mentioned preferred embodiments, it is possible to make various modifications or variations without departing from the spirit and scope of the invention. Accordingly, the appended claims will cover such modifications and variations as fall within the spirit of the invention.

Claims (4)

delete Forming a gate oxide film on the silicon substrate; Forming a gate electrode on the gate oxide film; Forming a source / drain region in the silicon substrate so as to be spaced apart from the gate electrode; Forming a wiring electrode electrically connected to the gate electrode and a source / drain region; And Ion implanting the ions into the gate oxide to increase the distribution of ions to prevent deterioration of the gate oxide at the interface between the gate oxide and the silicon substrate and to lower the distribution of the ions in the gate oxide; and, A method for manufacturing a semiconductor device, wherein any one of hydrogen ions and deuterium ions is ion implanted as the ions. delete The method of manufacturing a semiconductor device according to claim 2, wherein the ions are implanted at an energy of 30 to 100 KeV and an ion irradiation amount of 1E12 to 1E14 / cm ² .

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