JPS632511B2 - - Google Patents

Info

Publication number
JPS632511B2
JPS632511B2 JP56210400A JP21040081A JPS632511B2 JP S632511 B2 JPS632511 B2 JP S632511B2 JP 56210400 A JP56210400 A JP 56210400A JP 21040081 A JP21040081 A JP 21040081A JP S632511 B2 JPS632511 B2 JP S632511B2
Authority
JP
Japan
Prior art keywords
clock pulse
circuit
output
signal
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56210400A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58116830A (ja
Inventor
Tetsuo Inose
Masahiro Niino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
Original Assignee
NEC Home Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd filed Critical NEC Home Electronics Ltd
Priority to JP56210400A priority Critical patent/JPS58116830A/ja
Publication of JPS58116830A publication Critical patent/JPS58116830A/ja
Publication of JPS632511B2 publication Critical patent/JPS632511B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP56210400A 1981-12-30 1981-12-30 クロツクパルス発生回路 Granted JPS58116830A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56210400A JPS58116830A (ja) 1981-12-30 1981-12-30 クロツクパルス発生回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56210400A JPS58116830A (ja) 1981-12-30 1981-12-30 クロツクパルス発生回路

Publications (2)

Publication Number Publication Date
JPS58116830A JPS58116830A (ja) 1983-07-12
JPS632511B2 true JPS632511B2 (en, 2012) 1988-01-19

Family

ID=16588685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56210400A Granted JPS58116830A (ja) 1981-12-30 1981-12-30 クロツクパルス発生回路

Country Status (1)

Country Link
JP (1) JPS58116830A (en, 2012)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02133285U (en, 2012) * 1989-04-07 1990-11-06

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0732389B2 (ja) * 1989-09-22 1995-04-10 日本電気株式会社 クロツクジツタ抑圧回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02133285U (en, 2012) * 1989-04-07 1990-11-06

Also Published As

Publication number Publication date
JPS58116830A (ja) 1983-07-12

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