JPH0158898B2 - - Google Patents

Info

Publication number
JPH0158898B2
JPH0158898B2 JP56210401A JP21040181A JPH0158898B2 JP H0158898 B2 JPH0158898 B2 JP H0158898B2 JP 56210401 A JP56210401 A JP 56210401A JP 21040181 A JP21040181 A JP 21040181A JP H0158898 B2 JPH0158898 B2 JP H0158898B2
Authority
JP
Japan
Prior art keywords
clock pulse
output
signal
circuit
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56210401A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58116831A (ja
Inventor
Tetsuo Inose
Masahiro Niino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
Original Assignee
NEC Home Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd filed Critical NEC Home Electronics Ltd
Priority to JP56210401A priority Critical patent/JPS58116831A/ja
Publication of JPS58116831A publication Critical patent/JPS58116831A/ja
Publication of JPH0158898B2 publication Critical patent/JPH0158898B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Television Systems (AREA)
JP56210401A 1981-12-30 1981-12-30 クロツクパルス発生回路 Granted JPS58116831A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56210401A JPS58116831A (ja) 1981-12-30 1981-12-30 クロツクパルス発生回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56210401A JPS58116831A (ja) 1981-12-30 1981-12-30 クロツクパルス発生回路

Publications (2)

Publication Number Publication Date
JPS58116831A JPS58116831A (ja) 1983-07-12
JPH0158898B2 true JPH0158898B2 (en, 2012) 1989-12-14

Family

ID=16588700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56210401A Granted JPS58116831A (ja) 1981-12-30 1981-12-30 クロツクパルス発生回路

Country Status (1)

Country Link
JP (1) JPS58116831A (en, 2012)

Also Published As

Publication number Publication date
JPS58116831A (ja) 1983-07-12

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