GB2089601A - Phase Sensitive Detector - Google Patents

Abstract

A phase sensitive detector comprises four D-type flip-flops 701 to 704 which are so interconnected that in response to data pulses DP and clock pulses CK they produce respective pulse sequences D1 to D4. An exclusive OR-gate 705 receives the pulse sequences D2 and D3, and an exclusive OR-gate 706 receives the pulse sequences D1 and D4. Depending on the occurrence of the data pulses DP relative to the clock pulses CK, the pulse sequences D3 and D4 will occur early or late relative to the pulse sequences D1 and D2. As a result, the logic outputs from the gates 705 and 706 will proportionately control two current sources 708 and 709 of a current source circuit 707 to drive current into and extract current from a capacitor 203. The voltage across the capacitor 203 serves as a control voltage for synchronising the clock pulses CK, with the data pulses DP. <IMAGE>

Description

SPECIFICATION Phase Sensitive Detector This invention relates to a data pulse receiver arrangement of a type suitable for the acquisition of data pulses which occur in a serial bit stream in a received information signal in which one level of the signal (say high) represents a binary value '1' and another level of the signal (say low) represents a binary value '0', said arrangement including a data clock pulse generator for clocking the data pulses into the data pulse receiver arrangement. The invention relates more particularly to a phase sensitive detector in or for use in such data clock pulse generator.

A data pulse receiver arrangement of the above type (which is known for instance from Mullard Technical Information Article 34, dated September 1976, and Mullard Technical Information Article 54, dated August 1977) has application in data transmission systems in which data transmission and reception is not synchronised. Such a data transmission system is, for example, the BBC/IBA Teletext television transmission system in which coded data pulses representing aplha-numeric text or other message information are transmitted in a video signal in at least one television line in field-blanking intervals where no picture signals representing normal picture information are present. United Kingdom Patent Specification No. 1,370,535 discloses a television transmission system of this form.

A difficulty that occurs with such an application of the data pulse receiver arrangement is to synchronise clock pulses locally generated therein with the received coded data pulses. One technique for achieving this synchronisation is to generate a local data pulse clock from the received data pulses. A data clock pulse generator which is suitable for this purpose is a ringing circuit which comprises a tuned circuit arranged for oscillation at predetermined clock pulse frequency, together with means to produce current pulses in response to the received data pulses for exciting the tuned circuit to maintain its oscillation in synchronism with the received data pulses. Another technique for achieving said synchronisation is to generate a local data pulse clock independently of the received data pulses and then shift its phase into synchronism with them.A data clock pulse generator which is suitable for this latter purpose may comprise an osicllator arranged for oscillation at a predetermined clock pulse frequency to produce locally generated clock pulses, together with a phase sensitive detector which is operable to produce a control signal in accordance with the relative phases of the received data pulses and the clock pulses, which control signal is then used to correct the phase of the oscillator output to bring the data pulses and clock pulses into synchronism. The control exercised by the control signal may act directly on the oscillator (e.g, in the case of a voltage-controlled oscillator), so that the phase of the oscillator output, as actually produced, is corrected.Alternatively, the control exercised by the control signal may cause a phase shifter arrangement to alter the phase of the oscillator output after it has been produced. This latter form of control permits a highly stable oscillator, such as a crystal-controlled oscillator, to be used to generate the clock pulses.

It is an object of the present invention to provide an improved phase sensitive detector which is suitable for use in a data clock pulse generator in which synchronisation between received data pulses and locally generated clock pulses is achieved by bringing the phase of the clock pulses into synchronism with that of the data pulses.

According to the invention said phase sensitive detector includes a logical circuit arrangement which provides a first pair of logic output values pertaining to a first condition in which the clock pulses are earlier in phase than the data pulses, and a second pair of logic output values pertaining to a second condition in which the clock pulses are later in phase than the data pulses, the first condition being detected when the two values of said first pair are opposite (i.e.

1,0 or 0,1) and the second condition being detected when the two values of said second pair are opposite (i.e. 1,0 or 0.1).

Also, according to the invention there is provided a phase sensitive detector for use in a data clock pulse generator which comprises an oscillator arranged for oscillation at a predetermined clock pulse frequency to produce locally generated clock pulses, together with a phase sensitive detector which is operable to produce a control signal in accordance with the relative phases of received data pulses and the clock pulses, said control signal being used to correct the phase of the oscillator output to bring the data pulses and clock pulses into synchronism: which phase sensitive detector is characterised by comprising four logical circuits each having a data input, a clock input and a logic output and being operable in such manner that a binary logic value '1' or 'O' at its data input appears at its logic output on the application of a clock pulse at its clock input and remains at the logic output until the application of the next clock pulse, when the logic output then assumes the subsisting data input value until the next again clock pulse, of which logical circuits the first and the fourth have their clock inputs connected to receive said clock pulses and the second and the third have their clock inputs connected to receive an inverted version of said clock pulses, and of which the first and the third have their data inputs connected to receive said data pulses, while the logic output of the first is connected to the data input of the second and the logic output of the third is connected to the data input of the fourth, the logic outputs of the second and third logical circuits being connected to respective inputs of a first exclusive OR-gate and the logic outputs of the first and fourth logical circuits being connected to respective inputs of a second exclusive OR-gate, the outputs of these two gates being connected to means for producing said control signal in accordance with the logic values of these gate outputs.

In carrying out the invention, said means for producing said control signal may comprise a capacitor the charge across which determines the value of the control signal, together with two current sources which are controlled respectively by the two gate outputs for one logic value thereof to drive current into and extract current from the capacitor.

A phase sensitive detector as set forth above can be embodied in a data clock pulse generator in which locally generated clock pulses are generated by a crystal-controlled oscillator and are applied to a phase shifter which is controlled by said control signal to produce phase-corrected clock pulses.

In order that the invention may be more fully understood, reference will now be made by way of example to the accompanying drawings, of which~ Figure 1 shows a block diagram of a first form of data clock pulse generator; Figure 2 shows a block diagram of a second form of data clock pulse generator; Figures 3a to 3c show explanatory pulse waveforms and a coded pulse format; Figure 4 shows a resetting circuit for the data clock pulse generator of Figure 2; Figure 5 shows a timing circuit for the data clock pulse generator of Figure 2; Figure 6 shows a voltage-to-current converter circuit for the data clock pulse generator of Figure 2; Figure 7 shows a logic diagram of a phase sensitive detector; Figures 8a and 8b shows explanatory pulse waveforms for the detector of Figure 7; and Figure 9 shows a current source circuit for the phase sensitive detector of Figure 7.

Referring to the drawings, the data clock pulse generator shown in Figure 1 simply comprises a data clock pulse source 101, a phase sensitive detector 102 and a storage capacitor 103. A data slicer 104 receives data pulses DP from an input interminal 105. After level correction and possibly re-shaping (by suitable known means not shown), the data pulses DP are applied to an output lead 106 for utilisation in further circuitry, the pulses DP being clocked into this further circuitry by means of clock pulses CK which are applied to a clock pulse leas 107 by the source 101. The data pulses DP and the clock pulses CK are also applied to the phase sensitive detector 102 which is responsive thereto to produce a control signal CS on a control lead 108, this control signal CS having a d.c. value in accordance with the relative phase of the data pulses DP and the clock pulses CK.This control signal CS is used to vary the voltage across the capacitor 103 to provide a control voltage for correcting the phase of the source 101 so as to bring the clock pulses CK into synchronism with the data pulses DP. The source 101 can comprise in known manner a voltagecontrolled oscillator, together with means for limiting and squaring the output therefrom to form the clock pulses CK. The phase sensitive detector 102 takes the form shown in Figure 7, as will be described.

The data clock pulse generator shown in Figure 2 is more elaborate than that shown in Figure 1 and has a specific application in a data pulse receiver arrangement for the aforesaid BBC/IBA Teletext transmission system. This latter data clock pulse generator also comprises a data clock pulse source 201, a phase sensitive detector 202 and a storage capacitor 203, and a data slicer 204 receives data pulses DP from an input terminal 205 and feeds them to an output lead 206 for utilisation. Also, clock pulses CK are produced on a clock pulse lead 207, and a control signal CS is produced on a control lead 208.

There is also shown a limiter 209 for limiting (and squaring) the output from the soruce 201. In this instance the source 201 comprises a crystalcontrolled oscillator 210 and a phase shifter 211.

The oscillator 210 produces a highly stable alternating signal at the clock frequency and the phase shifter 211 is responsive in accordance with the d.c. value of the control signal CS to bring the oscillator output into phase synchronism with the data pulses DP. The phase shifter 211 can take any suitable known form, but preferably takes the form shown in our co-pending United Kingdom Patent Application No. 8039875. The phase sensitive detector 202 again takes the form shown in Figure 7, as will be described.

The data clock pulse generator of Figure 2 additionally comprises a re-setting circuit 212, a timing circuit 213 and a voltage-to-current converter circuit 214. Before considering the functions of these elements 212 to 214, which functions involve timing related to the coded data pulse transmission in the aforesaid BBC/IBA Teletext television transmission, a digression will now be made to explain certain transmission parameters with reference to Figures 3a to 3c.

Figure 3a shows a waveform diagram which represents a Teletext television video signal for one television line which occurs in a field-blanking interval and which includes coded pulse data. In this waveform diagram the line synchronising pulse for the television line concerned is represented at LS 1, and the line synchronising pulse for the next television line is represented at LS2. The colour burst on the television line concerned and that on the next television line, are represented at CB 1 and CB2, respectively.

Assuming the television broadcast standards for 625-line systems as employed in the United Kingdom, the period of one television line (i.e. the period between the leading edges of successive line synchronising pulses) is 64,us., as indicated.

Further assuming the standards adopted in the United Kingdom for information transmission by digitally coded pulses in the field-blanking intervals of such a 625-lien system (see "Broadcast Teletext Specification", September 1976, published jointly by the British Broadcating Corporation, Independent Broadcasting Authority and British Radio Equipment Manufacturer's Association), then the television line shown would by line number 17 or 18 in an even field and line number 330 and 331 in a odd field. Such a television line is referred to as a television data line and can contain coded data pulses representing 360 binary bits which may be considered as 45 eight-bit bytes. The position of the coded pulse data in the data line is indicated at CPD.The binary bit signalling rate is approximately 7 Mbit/s, and the binary bit signalling levels are defined between a black level BL and a peak white level WL. The binary '0' level is the black level BL and the binary %1- level is the level L.

Figure 3b shows a possible format for coded pulse data in a television data line. As mentioned above, the binary bits representing the coded pulse data are divided up into eight-bit bytes 1,2, 20.... The first two bytes 1 and 2 comprise a sequence of clock runin pulses which in the present example consist of a sequence of alternating bits 10101010/10101010. The third byte 3 comprises a framing or start code, e.g.

11100100, which a data pulse receiver arrangement has to identify before it will respond to accept message information which is contained in the remaining eight-bit bytes 4, 5 20....

Figure 3c shows in idealised form the first part of a video signal waveform VS for a television data line showing the sequence of clock run-in pulses CL and the sequence of pulses which comprise the framing code FR. The first few coded data pulses which represent alpha-numeric characters or other message information are shown at DP. The line synchronising pulse is represented at LS and the colour burst at CB.

Returning to Figure 2, the resetting circuit 212 is so organised in relation to the above coded data pulse transmission format that in each television data line it is operated by the line flyback pulse FL to connect a reference voltage RV across the capacitor 203 during the line blanking interval.

This reference voltage RV sets the voltage across the capacitor 203 to a value corresponding to the middle of the phase range afforded by the phase shifter 211. During the ensuing period that the sequence of clock run-in pulses CL of the video signal VS occurs, the timing circuit 213 supplies to the voltage-to-current converter circuit 214 a timing pulse T which causes this circuit 214 to substantially increase (e.g. double) its current output from a normal rate in response to the control signal CS (which it receives as a voltage) so that within this relatively short clock run-in period the control voltage across the capacitor 203 as produced by the current output of the circuit 214 can assume a mean value corresponding to the mean phase of the clock run-in pulses.For the remainder of the television data line, the circuit 214 operates to produce its current output at the normal, lower rate to provide a more stable control voltage about this mean value.

The re-setting circuit 212 can take the form shown in Figure 4, wherein it simply comprises a field-effect transistor 401 which is arranged as an electronic switch to connect the reference voltage RV across the capacitor 203 during the application of the flyback pulse FL to its gate electrode.

The timing circuit 213 can take the form shown in Figure 5, wherein it comprises a line synchronising pulse separator 501 and a pulse generator 502. The synchronising pulse separator 501 detects the line sync, pulses LS in the video signal VS to trigger the pulse generator 502 which is responsive to produce the timing pulse T by which the circuit 214 is operated. The pulse generator 502 includes a trigger delay such that the timing pulse T occurs at the beginning of the sequence of clock pulses CL and lasts for substantially the duration thereof.

The voltage-to-current converter circuit 214 can take the form shown in Figure 6, wherein it comprises two converting elements 601 and 602 connected in parallel, with an electronic switch 603 (suitably comprised bya field-effect transistor in similar fashion to the transistor 401 in Figure 4) connected in series with the element 602. During the period of the timing pulse T, which closes the switch 603, the control signal (voltage) CS is applied to both the elements 601 and 602 which thus both effect voltage-to-current conversion to feed current to the capacitor 203. When the switch 603 is open, only the element 601 is operative to feed current to the capacitor 203.

The elements 601 and 602 are incorporated in the current source circuit of Figure 9, as will be described.

The phase sensitive detector shown in Figure 7 comprises four D-type flip-flops 701 to 704, two exclusive OR-gates 705 and 706, and a current source circuit 707. Each of the flip-flops 701 and 704 has a data input D, a clock input CK and a logic output 0 (the other logic output Q is not used). The data pulses DP are applied to the Dinputs of flip-flops 701 and 703, the Q-output of flipflop 701 is connected to the D-input of flipflop 702, and the Q-output of flip-flop 703 is connected to the D-input of flip-flop 704. As regards the clock pulses CK, these are applied directly to the CK-inputs of flip-flops 701 and 704 and, after inversion by an inverter 710, to the CKinputs of flip-flops 702 and 703.The Outputs of flip-flops 701 and 704 are connected to respective inputs of the exclusive OR-gate 706 and the Q-outputs of flip-flops 702 and 703 are connected to respective inputs of the exclusive OR-gate 705. The outputs of the gates 705 and 706 are connected respectively to two current sources 708 and 709 in the circuit 707. There is also shown in Figure 7 the capacitor 203 across which the control signal voltage CS is produced.

Consider now the operation of the phase sensitive detector of Figure 7 with reference also to the explanatory pulse waveforms shown in Figures 8a and 8b. Ideally, for clocking the data pulses DP into a data pulse receiver arrangement, an edge of the clock pulses CK should occur in the centre of a data pulse. This relationship, in which the clock pulses are in phase synchronism with the data pulses, is indicated in Figure 8a by the broken line IPH which shows the rising edge of a clock pulse occurring at the centre of a data pulse.

Thus, as regards the phase sensitive detector of Figure 7, this relationship results in the pulse sequence D1 at the Q-input of the flip-flop 701 being delayed by one half a clock pulse period relative to the data pulse DP at the D-input of this flip-flop. Since the flip-flop 702 is clocked by the inverted clock puises CK, the pulse sequence D2 at the Q-output of the flip-flop 702, in response to the pulse sequence D1 at its D-input, is similarly delayed by one half a clock pulse period relative to the pulse sequence D1.This half a clock pulse period phase relationship between the pulse sequence D1 and the pulse sequence D2 remains constant irrespective of any shift in the relative phase of the data pulses DP and the clock pulses CK which varies the relative phase of the data pulses DP and the pulse sequence D1.

However, this relative phase of the data pulses DP and the clock pulses CK does affect the production of the pulse sequence D3 by the flipflop 703 and the production of the pulse sequence D4 by the flip-flop 704, as will now be considered. Consider first the case where the clock pulses CK are later (L) in phase than the data pulses DP, so that the rising edge RE1 of the inverted clock pulses CK occurs after the rising edge RE of the data pulses DP. The effect of this is to cause the flip-flop 703 to start the pulse sequence D3 with the rising edge L1.On the other hand, if the clock pulses CK are earlier (E) in phase than the data pulses DP, so that the rising edge RE1 of the inverted clock pulses CK occurs before the rising edge RE of the data pulses DP, the pulse sequence D3 will not start until its rising edge El,when the rising edge RE2 of the inverted clock pulses CK occurs. If the pulse sequence D3 occurs early at L1, then the pulse sequence D4, as produced by the flip-flop 704, also occurs early at the rising edge L2 when the next rising edge of the clock pulses CK occurs, whereas if the pulse sequence D3 occurs late at E1, then the pulse sequence D4 also occurs late at the rising edge E2 when the next again rising edge of the clock pulses CK occurs.

Consideration of the logic levels of the pulse sequences D1 to D4 will show that when the clock pulses CK are later in phase than the data pulses DP, D3 is high when D2 is low, and both D1 and D4 are high together, so that the exclusive OR-gate 705 output is high; whereas when the clock pulse CK are earlier in phase than the data pulses DP, D1 is high when D4 is low, and both D2 and D3 are low together, so that the exclusive OR-gate 706 output is high. The output from exclusive OR-gate 705 controls the current source 708 to drive current into (charge) the capacitor 203 and the output from the exclusive OR-gate 706 controls the current source 709 to extract current from (discharge) the capacitor 203.The charge on the capacitor 203 and hence the value of the control signal voltage CS is therefore being continuously altered to tend to bring the clock pulses CK into synchronism with the received data pulses DP. Figure 8b merely serves to illustrate that the phase sensitive detector of Figure 7 can also function as described above to effect phase synchronism between the rising edge of the clock pulses CK and the centre of the "low" portion of the data pulses DP. In this alternative, the pulse sequences Dl to D4 would be produced at the u outputs of the flip-flops 701 and 704.

The current source circuit 707 in Figure 7 can take the form shown in Figure 9, wherein it comprises two transistor pairs 901/902 and 903/904 of opposite conductivity type, both pairs being connected as current mirrors. The transistors 902 and 904 are connected in push pull with their collectors connected together and to the capacitor 203. The collectors of the other two transistors 901 and 903 are fed, respectively, with voltage pulses 905 and 906 which constitute the outputs from the exclusive OR gates 705 and 706 in Figure 7. An inverter 907 inverts the pulses 905 to form pulses 905'. Two resistors 908 and 909 determine the current magnitude that flows in the transistors 901 and 903 in response to the voltage pulses 905 and 906. The resultant push-pull current in the transistors 902 and 904 adjusts the charge on the capacitor 203.In order to provide increased current into the capacitor circuit during the period of the clock run-in pulses CL (Figure 3c), as mentioned previously when Figure 2 (and Figure 6) was being described, there is provided as shown in the dotted line rectangle 910 a second current source circuit which is fed with the voltage pulses 905 and 906. However, the output at the collectors of the push-pull transistor pair in this second current source circuit is connected to the capacitor 203 via a field-effect transistor 911 which functions as a switch in response to the timing pulse T, so that the capacitor 203 receives current from this second current source circuit only for the duration of this timing pulse T. The current due to the second current source can be proportionally different to that due to the first current source by suitable selection of the values of the resistors such as 908 and 909 in the second current source.

Claims (11)

Claims

1. A phase sensitive detector for use in a data clock pulse generator in which synchronisation between received data pulses and locally generated clock pulses is achieved by bringing the phase of the clock pulses into synchronism with that of the data pulses, said phase sensitive detector being characterised in that it includes a logical circuit arrangement which provides a first pair of logic output values pertaining to a first condition in which the clock pulses are earlier in phase than the data pulses, and a second pair of logic output values pertaining to a second condition in which the clock pulses are later in phase than the data pulses, the first condition being detected when the two values of said first pair are opposite and the second condition being detected when the two values of said second pair are opposite.

2. A phase sensitive detector for use in a data clock pulse generator which comprises an oscillator arranged for oscillation at a predetermined clock pulse frequency to produce locally generated clock pulses, together with a phase sensitive detector, which is operable to produce a control signal in accordance with the relative phases of received data pulses and the clock pulses, said control signal being used to correct the phase of the oscillator output to bring the data pulses and clock pulses into synchronism; which phase sensitive detector is characterised by comprising four logical circuits each having a data input, a clock input and a logic output and being operable in such manner that a binary logic value '1' our '0' at its data input appears at its logic output on the application of a clock pulse at its clock input and remains at the logic output until the application of the next clock pulse, when the logic output then assumes the subsisting data input value until the next again clock pulse, of which logical circuits the first and the fourth have their clock inputs connected to receive said clock pulses and the second and the third have their clock inputs connected to receive an inverted version of said clock pulses, and of which the first and the third have their data inputs connected to receive said data pulses, while the logic output of the first is connected to the data input of the second and the logic output of the third is connected to the data input of the fourth, the logic outputs of the second and third logical circuits being connected to respective inputs of a first exclusive OR-gate and the logic outputs of the first and fourth logical circuits being connected to respective inputs of a second exclusive OR-gate, the outputs of these two gates being connected to means for producing said control signal in accordance with the logic values of these gate outputs.

3. A phase sensitive detector as claimed in Claim 2, wherein said means for producing said control signal comprises a capacitor the charge across which determines the value of the control signal, together with two current sources which are controlled respectively by the two gate outputs for one logic value thereof to drive current into and extract current from the capacitor.

4. A phase sensitive detector as claimed in Claim 3, wherein said two current sources are comprised by two transistor pairs of opposite conductivity type, both pairs being connected as current mirrors, the input transistor of each pair being connected to receive at its collector the logic output from a respective one of said two gates, one output with polarity inversion, and the other two transistors, one from each pair, being connected in push-pull with their collectors connected together and to said capacitor, a respective resistor for determining the current magnitude in each current mirror transistor pair being connected between the collector of its input transistor and the respective gate output.

5. A phase sensitive detector as claimed in Claim 2, Claim 3 or Claim 4, arranged to effect phase synchronism between the rising edge of the clock pulses and the centre of the "high" portion of the data pulses.

6. A phase sensitive detector as claimed in Claim 2, Claim 3 or Claim 4, arranged to effect phase synchronism between the rising edge of the clock pulses and the centre of the "low" portion of the data pulses, by using inverted logic outputs from the first and fourth logical circuits.

7. A phase sensitive detector as claimed in any one of Claims 2 to 6, embodied in a data clock pulse generator in which the locally generated clock pulses are generated by a voltage-controlled oscillator which is controlled by said control signal to produce phase-corrected clock pulses.

8. A phase sensitive detector as claimed in any one of Claims 2 to 6, embodied in a data clock pulse generator in which the locally generated clock pulses are generated by a crystal-controlled oscillator and are applied to a phase shifter which is controlled by said control signal to produce phase-corrected clock pulses.

9. A phase sensitive detector substantially as hereinbefore described with reference to Figures 7 and 8a, or 7 and 8b, of the accompanying drawings.

10. A phase sensitive detector as claimed in Claim 9, having a current source circuit substantially as hereinbefore described with reference to Figure 9 of the accompanying drawings.

11. A phase sensitive detector as claimed in Claim 9 or Claim 10, embodied in a data pulse generator substantially as hereinbefore described with reference to Figure 1 or Figures 2 to 6 of the accompanying drawings.