JPS63250861A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To perform a high speed operation by forming a drain region and a reverse conductivity type conductive layer to the drain region only on the lower part of an operating layer to reduce a drain capacity. CONSTITUTION:A second insulating film 16 and an organic or inorganic film 17 having viscosity are formed on a gate electrode pattern in which a gate electrode 12 and a first insulating film 13 are laminated, flattened on the surface, the film 13 is then exposed by dry etching at an equal speed, and the film 13 is selectively removed. Thereafter, with the film 16 as a mask except the gate 12 an impurity for forming a reverse conductivity type to an operating layer 11 is ion implanted through the electrode 12 and the layer 11 to form a reverse conductivity type conductive layer 18 only on the lower part of the layer 11. Thus, a part for forming the inner junction of one conductivity type region 15 of the drain is limited only to the end of the gate to largely reduce a junction area, thereby suppressing a junction capacity.

Description

[Detailed description of the invention] [Object of the invention].

(Industrial Application Field) The present invention relates to a method for manufacturing a Schottky junction gate field effect transistor using a compound semiconductor as a substrate.

(Prior Art) There are two methods for improving the performance of a Schottky junction gate field effect transistor (hereinafter abbreviated as MESFET) using GaAs as a substrate.

■ Shorten the gate length.

■ Make the active layer thinner or more concentrated.

However, when the gate length is shortened, the highly doped source/drain regions formed on both sides of the gate are close to each other, so current flows between them through the substrate, and the threshold voltage (Vth) increases. A so-called sea channel effect occurs in which the transconductance g is shifted to the negative side and the mutual conductance g is degraded. In addition, when thinning the active layer, generally
The active layer of aAs MESFET is formed by ion implantation, and there are restrictions from the ion implantation equipment itself in order to reduce the implantation energy and make the active layer thinner.5 As a way to solve these problems, the active layer A technique has been reported to form a p-type layer of the opposite conductivity type below an n-type layer (K, Yamasaki at.

al,, ”Below 10 ps/gate 0p
eration tzith Buriedp-1ay
er SA ENG TFE"1."'s" Elect
ronj, csLettere Vol, 20pp
1029-1031.1984).

The structure of the MESFET shown in this document is shown in FIG. In this MESFET, a highly doped n+ type source and drain region (42) is provided adjacent to the gate electrode (45).

(43) is formed. and n-type operating layer (41)
Extends. (46) and (47) are source and train electrodes, (48) is a SiN film, and (49) is a 5 inch
In the MESF [ET], which has a two-film zero-layer structure, a p
The type layer (44) is an n-type source.

It acts as a potential barrier for electrons between the drain regions (42) and (43), prevents substrate current from flowing, and suppresses the short channel effect. Furthermore, this p-type layer (4
4) forms a p-n junction with the active layer (41), and the built-in current extends a depletion layer to the active layer (41) side, substantially making the active layer (41) thinner. ing.

However, in this structure, since the p-type layer (44) also forms a p-n junction with the drain region (43), there is a drawback that the drain current capacitance to ground increases. In addition, for GaAs MESFET bonding, generally an AuGe alloy is reacted (alloyed) with [1aAs] as an ohmic electrode.
This will form an ohmic contact.

This alloying reaction proceeds to a considerable depth. As a result, the source/drain electrodes (46) and (47) come into contact with the p-type layer (44), and the potential of the p-type layer (44), which should originally be floating, is modulated by the source or drain voltage. There is also a risk of changing the threshold value.

Furthermore, in an attempt to solve these problems, the p-type layer is made thinner than each n-type region. Or each n+ type region p
If a method is adopted in which the layer is formed deeper than the type layer, a substrate current will flow between each n+ type region under the p type layer, making it impossible to sufficiently suppress the short channel effect.

(Problems to be Solved by the Invention) As described above, the conventional manufacturing method cannot sufficiently suppress the short channel effect, and there is a variation in the threshold value, and the ME
There was a problem that the yield of SFET was poor.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a field effect transistor with a high yield, which can sufficiently suppress the short channel effect and have less fluctuation in threshold value.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, in the present invention, - an active layer of a conductivity type, a source, a drain region, and an opposite conductivity type conductive layer of an opposite conductivity type are formed under the active layer. A second insulating film and a second insulating film are formed on the gate electrode pattern in which the insulating films of the gate electrode cylinder 1 are laminated as a means for realizing a field effect transistor having a structure in which the field effect transistor is provided only in the source and drain regions and is not in contact with the one conductivity type region of the source and drain. A viscous organic or inorganic film is formed to flatten the surface, and then the surface of the first insulating film is exposed by constant speed dry etching, and the first insulating film is selectively removed. After this, by using the second insulating film as a mask except for the gate part, ions of impurities forming the opposite conductivity type to that of the active layer are implanted through the gate electrode and the active layer, so that only the lower part of the active layer has conductivity of the opposite conductivity type. It is characterized by forming layers.

(Function) The capacitance of a junction between one conductivity type and the opposite conductivity type is proportional to the area of the junction. In this structure.

Since the portion forming the internal platform of one conductivity type region of the drain is limited to only the gate end, the junction area is significantly reduced compared to the conventional structure, and as a result, the junction capacitance can be suppressed.

Further, since there is no stack of opposite conductivity types under the ohmic electrode, even if the ohmic electrode penetrates through the source and drain regions of one conductivity type due to an alloying reaction, it will not come into contact with the conductive layer of the opposite conductivity type.

Furthermore, since the opposite conductivity type layer is provided by ion implantation from above a mask of a thick and vertically patterned insulating film, it becomes a layer in which impurities are distributed at a designed depth. Therefore, since a layer of the opposite conductivity type can be formed under the active layer with good controllability, a MESFET exhibiting a stable threshold value can be formed with a high yield.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the ME obtained by the method of one embodiment of the present invention.
It is a sectional view of SFET.

An n-type active layer (
11) is formed, and a gate electrode (12) is formed on top of it. Close to this gate electrode (12).

An n+ type source with higher concentration and deeper depth than the n type operating layer (11).

Drain regions (14) and (15) are formed of self-aligned lines. A p-type RIJ (18) having a conductivity type opposite to that of the operation layer is formed below the n-type operation layer (11), but this PI! :1FPI (18) is the operational layer (1
1) is formed only under the source and drain regions.
Biotype area (14).

(15) is not formed at the bottom of (19),
(20) are source and drain electrodes, respectively.

Next, a manufacturing method for realizing the structure shown in FIG. 1 will be explained using FIG. 2.

Si ions were implanted into a semi-insulating GaAs substrate (IO) at an acceleration energy of 50 KeV. OX 10”
cm-” and injected selectively at 82 cm in an arsine atmosphere.
By heat treatment at 0°C for 20 minutes, the n-type operating layer (
]1).

Next, as a heat-resistant gate electrode, a tungsten nitride (WNx) film (12) was deposited to a thickness of 1000 nm by reactive sputtering, and p-CVD (Plasma act
ivatedChemical Vapor Dep
SiOx film (13)
Form to the thickness of a person. A gate electrode pattern was formed using a photoresist (not shown) using a known lithography technique, and using this resist as a mask, 5 lots of + WNx were etched by reactive ion etching (RIE) using a mixed gas of CF4 + H, and CF4 + O□. ) to form a gate electrode pattern consisting of 5ins (13)/WNx (12) (FIG. 2(a)).

Using this 5iOz (13)/1INx (12) pattern as a mask, S1 ions were accelerated at an energy of 120K.
By implanting at eV, implantation dose 3, and OX 10"ts-", high concentration, low resistance n◆ type source and drain regions (14) and (15) are self-aligned to the gate electrode (12). (Fig. 2(b)).

Next, p-CVD the whole surface Ni siN film (16)
Deposit and apply photoresist (17) to a thickness of 0.000 mm.

The SiN film (16) has excellent step coverage, and film formation proceeds faithfully to the shape of the underlying steps. On the other hand, the photoresist (17) is thick in flat areas due to its viscosity.

Further, the upper protruding portion of the gate electrode (12) is formed thinner, and its surface is flattened (FIG. 2(c)).

Continuing, CF, and 0. Using a mixed gas, the entire surface of the photoresist (17) is etched by RIE under conditions such that the etching speed of 5iN (16) is almost the same, and the etching is stopped when the upper part of the 5in2 film (13) is exposed. (Figure 2(d)).

After that, Be ions for forming a p-type layer are implanted into the entire surface at an acceleration energy of 100 KeV and an implantation amount of 7.times.10 "am-".

At this time, under these ion implantation conditions, Be ions are absorbed into the WNx film (12) and n in the opening where the SjO film is removed.
The p-type layer (18) penetrates through the n-type active layer (11) and forms n-type source and drain regions (18) under the n-type active layer (11).
14).

(15) Although the Be ions are formed deeper, in other parts, the 5,000-layer thick SiN film (16) serves as a mask for ion implantation, and the Be ions do not reach the GaAs substrate (10) (Fig. 2(e)). ).

Thereafter, the SiN film (16) is removed, and heat treatment is performed at 800°C for 20 minutes in an arsine atmosphere to form n÷ type source and drain regions (14), (15) and p type layer (1).
8) to activate the ions in the source and drain regions (14).
).

(15) Form source and drain ohmic electrodes (19) and (20) made of AuGe/Au on the FE
Complete T (Figure 2(f)).

MEiS-F obtained by the method of one embodiment of the present invention
In ET, there is no p-type layer below the n-type source and drain regions, and the n-type source and drain regions and the p-type layer contact only a portion on the active layer side. Therefore, the drain capacitance hardly increases compared to a conventional structure without a p-type layer.

Further, the device characteristics will not deteriorate due to penetration due to the alloying reaction of the ohmic electrode. Further, below the active layer, a p-type layer is formed deeper than the n-type source and drain regions. Since this p-type layer acts as a potential barrier against electrons, the gate length becomes short, and even if the n-type source and drain regions are close to each other, current flowing between these regions can be blocked. As a result, the gate length is reduced to 1
Even if the time is shortened to less than μs, no short channel effect occurs and a high-performance FET can be obtained. Further, this p-type layer forms a p-n junction with the n-type active layer, and its built-in potential causes a depletion layer to extend to the active layer side, effectively reducing the thickness of the active layer. Therefore, a highly concentrated thin active layer can be obtained without performing low-energy implantation, and the current driving ability of the FET is greatly improved.

Further, in the present invention, it is easy to reduce the gate resistance, and the details thereof will be explained as a second embodiment with reference to FIG. 3.

After the step shown in FIG. 2(a), the SiN film (16),
800°C in an N2 atmosphere chamber using the WNx film (12) as a protective film.
A heat treatment is performed for 20 minutes at °C to activate the implanted ions. After this, Ti/Pt/Au was applied to the entire surface at a rate of 1000/10, respectively.
Gate electrode (12) formed to a thickness of 0.15 million
Mask gate electrode (12
) is formed at the center, and unnecessary portions of metal are removed by ion milling to form a gate overlay electrode (32a) (FIG. 3(a)).

The method according to this embodiment obtains the same effects as those of the previous embodiment, but also has the following effects.

In other words, the gate resistance is reduced to 0.05Ω/gate, which is about 1/300, compared to the gate resistance of about 15Ω/hole when the gate electrode is only a 1000-layer νNX film (12), and is suitable for microwave devices, etc. When used, the high frequency characteristics are significantly improved.

Note that the formation of the gate overlay electrode (32b) is as follows.
This is performed after forming the ohmic electrodes (19) and (20), depositing the interlayer insulating film (33), and opening the contact hole.

As shown in FIG. 3(b), it is also possible to form metal wiring at the same time, which simplifies the process.

〔Effect of the invention〕

As described above, according to the present invention, since the drain region and the conductive layer of the opposite conductivity type are in contact with each other at a small surface, the drain capacitance is small, so high-speed operation is possible. Since it does not come into contact with the opposite conductivity type conductive layer, it exhibits a stable threshold value that is unlikely to cause potential modulation.

Field effect transistors can be obtained with high yield.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the structure of an MHSFET obtained by the method of the present invention, and FIG.
FIG. 3 is a sectional view showing the process of ESFET, FIG. 3 is a sectional view showing a MESFET according to another embodiment of the present invention, and FIG. 4 is a sectional view showing the structure of a conventional MESFET.

Claims (4)

[Claims] (1) Forming an active layer of one conductivity type on a semi-insulating compound semiconductor substrate, laminating a metal constituting a Schottky barrier and a first insulating film on the active layer, and patterning this laminated film. ion implantation using the gate electrode pattern as a mask to form highly doped source and drain regions of the same conductivity type as the active layer; a step of depositing an insulating film; and a step of applying a coating film made of a viscous organic or inorganic substance on the second insulating film;
etching the second insulating film and the coating film at substantially the same rate and stopping the etching when the top of the first insulating film is exposed; and selectively removing the first insulating film. and a step of ion-implanting an impurity to form a layer of a conductivity type opposite to that of the active layer through the gate electrode and the active layer using the second insulating film as a mask. A method for manufacturing a field effect transistor. (2) The method for manufacturing a field effect transistor according to claim 1, wherein the compound semiconductor substrate is GaAs. (3) The method for manufacturing a field effect transistor according to claim 1, wherein the coating film is a photoresist. (4) The operating layer, the source region, and the drain region are of n-type conductivity, and the conductive layer of the opposite conductivity type is p-type.
Claim 1 characterized in that the conductivity type is
A method for manufacturing a field effect transistor according to section 1.