JP2983663B2 - Epitaxial substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an epitaxial substrate suitable for use in a field effect transistor.

[0002]

2. Description of the Related Art With the development of a highly information-oriented society, an ultra-high-speed communication system is required. In order to construct this type of system, a semiconductor device that operates at a very high speed and consumes low power is required. There are many compound semiconductor devices such as GaAs that satisfy these requirements, and ultra-high-speed / ultra-high-frequency devices using compound semiconductors and integrated circuits thereof have been energetically studied.

An integrated circuit using GaAs (GaAsI
In the case of C), in order to improve the performance, it is necessary to improve the current driving capability of a field effect transistor (FET) which is the basic element.

As a promising technique for improving the current driving capability of FETs, a high-concentration thinning of an operation layer has been proposed.
By using this technique, the transconductance (g
_m ) and suppression of the two-dimensional electric field effect (short channel effect) which is remarkably observed in the FET having the submicron gate electrode.

[0005] When producing a high-concentration thin operating layer, ion implantation is widely used, but generally it is necessary to lower the implantation energy. In fact, it has been reported that an extremely high-performance MESFET having a maximum transconductance of 630 mS / mm has been obtained by realizing high-concentration thinning of the operating layer by low-energy and high-dose implantation (K Onodera et.al IEEE
Trans. Electron Devices Le
ters vol. 9 No. 8, 1988 p. 4
17-P. 418).

[0006]

In order to complete the working layer by the ion implantation method, it is necessary to activate the implanted donor pant by a heat treatment. The activation rate of the donor punt is reduced. In particular, the activation rate at the site where the concentration of the donor punt is high is low. In other words, the carrier is saturated at a portion where the concentration of the donor punt is high, and a desired carrier profile cannot be obtained.

[0007] Therefore, even the above-mentioned conventional MESFET is manufactured using low-energy implantation, so that the above-mentioned problem is included and its performance is limited.

The present invention has been made in view of the above circumstances, and has as its object to provide an epitaxial substrate capable of obtaining a desired carrier profile even with low energy implantation.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
A plurality of semiconductor layers activation rate are different are laminated, and, e ion implantation have been made on the plurality of semiconductor layers
A plurality of semiconductor layers, wherein the plurality of semiconductor layers are
The 1 GaAs layer, the InGaAs layer, and the second GaAs layer are
An epitaxial substrate, which is a stacked layer, wherein Si is ion-implanted .

[0010]

A desired carrier profile is achieved by arranging a semiconductor layer having a high activation rate in a portion of the epitaxial substrate where high concentration is required and arranging a semiconductor layer having a low activation rate in other portions. can do.

For example, the InGaAs layer has a higher critical concentration of Si donor than the GaAs layer,
Focusing on the fact that the nGaAs layer has a higher activation rate than the GaAs layer, the nGaAs layer is formed by laminating a GaAs layer, an InGaAs layer, and a GaAs layer in this order, and SiGaAs is ion-implanted into these layers to form InGaAs. The concentration of only the layer portion can be increased. Therefore, by arranging the InGaAs layer at a portion where the carrier concentration is to be increased, that is, at a portion where the peak of the carrier concentration is to be obtained, the InGaAs layer has a high concentration and a thin layer as compared with the case where the semiconductor layer is formed of a single GaAs layer. Operating layers can be formed.

[0012]

EXAMPLE On a GaAs substrate 1, 8000 DEG GaAs was formed.
Layer 2, 300 Ｉｎ InGaAs layer 3, 200 Ｇａ GaAs
The s layer 4 is stacked in this order, and Si is implanted at an energy of 30.
Ion implantation is performed under the conditions of keV and a dose of 2 × 10 ¹³ cm ⁻² . Then, an SiN film is formed on the entire surface of the substrate, and cap annealing is performed at 850 ° C. for 5 seconds using this film as a cap. Note that the In composition ratio of the InGaAs layer 3 is G
The configuration was such that the slope was from 0.15 to 0 from the aAs layer 2 to the surface side.

On the epitaxial substrate (A-1: FIG. 1) completed in this way, a GaAs layer is formed on a GaAs substrate as shown in FIG. 2, and ion implantation and annealing are performed under the same conditions as described above. Completed epitaxial substrate (B-
It can be seen that the carrier concentration near the peak is higher than in 1). That is, assuming that these substrates are used for the FET, the epitaxial substrate (A-1) has a thinner active layer than the epitaxial substrate (B-1).

Next, on the GaAs substrate 1, a GaAs layer 2 of 8000Å, an InGaAs layer 3 of 300Å, 200Å
Are deposited in this order, and Si ions are implanted under the conditions of an implantation energy of 30 keV and a dose of 6 × 10 ¹² cm ⁻² . Then, a SiN film is formed on the entire surface of the substrate,
Using this film as a cap, a cap annealing is performed at 850 ° C.
An epitaxial substrate (A-
2) A GaAs layer 9 is formed on the GaAs substrate 1 and ion implantation and annealing are performed under the same conditions as described above. A gate electrode 5 having a length of 6 μm, and a source electrode 6 and a drain electrode 7 on both sides of the gate electrode 5.
A GaAs MESFET provided with was manufactured and various evaluations were made. A contact layer 8 is provided under the source electrode and the drain electrode on both sides of the gate electrode. The contact layer 8 is formed by ion implantation.
0 keV and a dose of 4 × 10 ¹³ cm ⁻² . Also,
The In composition ratio of the InGaAs layer 3 was inclined from 0.15 to 0 from the GaAs layer 2 to the surface.

A GaAs MESFET (C: FIG. 3) completed using an epitaxial substrate (A-2) and a GaAsM completed using an epitaxial substrate (B-2: FIG. 4)
Various characteristics of ESFET (D) were measured. The measurement results were as follows.

[0016] GaAs MESFET (C), the maximum transconductance g _mmax is 420 ms / mm maximum K value K _max is 340 ms / Vmm threshold V _th is -0.62V drain conductance g _d is 28 ms / mm maximum cut-off frequency f _T Has a maximum mutual conductance g _mmax of 320 mS / mm, a maximum K value K _max of 260 mS / Vmm, a threshold V _th of -0.6 V, a drain conductance g _d of 50 mS / mm, and a maximum cutoff frequency f _T of 38 GHz GaAs MESFET (D). 26 GHz Looking at g _mmax , K _max , and V _th , the GaAs MES
It can be understood that the FET (C) has more excellent current driving capability.

Further, g _d is GaAs MESFET (C)
Is lower than that of InGaAs layer 3 / GaAs.
It can be understood that the so-called short channel effect is also reduced by the potential barrier at the interface of the s layer 2. This is achieved by forming a heterojunction between each semiconductor layer as in the embodiment of the present invention.

Although a substrate having a heterojunction is used in the above embodiment, the present invention can be applied to a substrate having a homojunction. That is, p ⁻ between the GaAs substrate 1 and the GaAs layer 2 of the epitaxial substrate (B-2).
Even when a substrate in which a GaAs layer is inserted is used, the carrier profile is _sharpened and g _mmax is improved due to the difference in the activation rate of the _dopant .

[0019]

According to the epitaxial substrate of the present invention, a desired carrier profile, in particular, a highly-concentrated thin injection layer can be obtained even with low-energy injection.

Therefore, the FET manufactured using the epitaxial substrate of the present invention has a high-concentration thin operating layer,
Extremely high performance.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of an epitaxial substrate according to one embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a distance from a substrate surface and a carrier concentration.

FIG. 3 is a schematic sectional view of a MESFET.

FIG. 4 is a schematic sectional view of a MESFET.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 GaAs substrate 2 GaAs layer 3 InGaAs layer 4 GaAs layer 5 Gate electrode 6 Source electrode 7 Drain electrode 8 Contact layer 9 GaAs layer

Claims (2)

(57) [Claims] To 1. A semiconductor substrate, a plurality of semiconductor layers activation rate are different are laminated, and, an epitaxial substrate where the ion implantation is performed on the plurality of semiconductor layers,
The plurality of semiconductor layers include a first GaAs layer, InGaAs
Layer and a second GaAs layer are sequentially stacked, and
An epitaxial substrate, wherein i is ion-implanted . 2. The InGaAs layer according to claim 1, wherein the composition ratio of In is
Inclined from large to small from the first GaAs layer side to the surface
2. The epitaxial substrate according to claim 1, wherein