JPH06275654A - Field effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To provide a field effect transistor suitable for integration wherein short channel effect can be restrained and, at the same time, interference between elements which is caused by the side gate effect can be restrained. CONSTITUTION:Ions are implanted into a potential barrier layer 200. The pattern of photoresist which has been used when the ions are implanted into the potential barrier layer 200 is isotropically etched. After ions are implanted into a channel layer 300, a source, a drain and a gate are formed in a self-alignment manner. The potential barrier layer 200 of a conductivity type different from the channel layer 300 is formed only in the part just under the channel layer 300, so that the short channel effect and the side gate effect can be effectively restrained, and a Schottky junction type field effect transistor element capable of integration can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor using a compound semiconductor and a method for manufacturing the same.

[0002]

2. Description of the Related Art A compound semiconductor device typified by a GaAs device has a high electron mobility because a band structure is a direct transition type, and a heterojunction can be easily realized. , Has been widely applied to the field of high-speed devices such as optical devices and high-frequency devices, and integration of compound semiconductor devices having high-speed operability has been attempted.

SA is a method for realizing such integration.
INT (Self-Aligned Implantation for n ⁺ -layer T
echnology). This technology uses a Schottky gate field effect transistor (ME) having a self-aligned structure.
SFET) is one of the manufacturing methods, in which n ⁺ layer ion implantation is performed using a dummy gate (not a Schottky metal gate) formed of a multilayer resist or the like as a mask, and after activation high temperature annealing treatment, a dummy gate trace is formed. It is a method of forming a metal gate by vapor deposition or the like. In this method, the source region and the gate region are self-aligned with the gate electrode, and a product having a gate length of 0.1 μm can be manufactured. However, the ME formed by SAINT
When the gate length of the SFET becomes approximately submicron and the distance between the source n ⁺ layer and the drain n ⁺ layer becomes narrower, it passes through the inside of the substrate which is the semi-insulating layer (i layer) below the channel layer which is the gate. A short-channel effect in which a substrate-side leak current that flows over the potential barrier of the n ⁺ in ⁺ structure flows and the gate voltage (threshold voltage) that cuts off the current shifts to the negative side becomes remarkable.

While suppressing this short channel effect, SAI
In order to apply a fine structure made of NT, a method is known in which a p-layer is provided on the substrate side by ion implantation and a potential barrier between n ⁺ layers is increased to suppress a leak current. Figure 4
FIG. 3 is a configuration diagram of a MESFET formed by adopting this method. As shown in the figure, this MESFET comprises a substrate 100 made of GaAs crystal having semi-insulating properties, a source region 410 and a drain region 420 containing a high concentration of an n-type dopant, and a source region 410 and a drain region 420. N-type channel layer 300 formed between
On the surface of the source region 410, the drain region 420, and the channel layer 300, the p-type barrier layer 250 formed on the substrate inner side, the source electrode 510 formed on the surface of the source region 410, and the surface of the drain region 420. The drain electrode 520 is formed and the gate electrode (Schottky electrode) formed on the surface of the channel layer 300. An insulating layer is formed between the electrodes.

This MESFET is manufactured, for example, as follows. First, n layer ions (Si ions, 6
0 keV, 2 to 3.2 × 10 ¹² / cm ² ) is implanted into the semi-insulating substrate 100 (GaAs), and then p-layer ions (Be ions, 90 keV, 6 × 10) are implanted using the same implantation mask.
¹¹ / cm ² ) is injected. Next, an n ⁺ layer ion implantation mask is formed, and n ⁺ layer ions (Si ions, 200 ke
V, 4 × 10 ¹³ / cm ² ) is injected. Then n layers,
The p layer and the n ⁺ layer are simultaneously subjected to activation annealing at 800 ° C. for 20 minutes. Subsequently, an ohmic electrode is formed on the surface of the n ⁺ layer and a Schottky electrode is formed on the surface of the n layer.

It is possible to prevent an increase in parasitic capacitance by selecting a condition in which the thickness and concentration of the p layer are just depleted by the np junction built-in potential with the channel layer (n layer).

[0007]

Since the conventional field effect transistor is constructed as described above, the short channel effect, which is a problem when the field effect transistor element is miniaturized, is effectively suppressed. There has been a problem that inter-element interference that occurs as a result of elements becoming close to each other due to integration increases. This problem is a phenomenon known as the "side gate effect" (Ohno et al .:
"Side Gate Effect in GaAs IC", Applied Physics, Vol. 61, No. 2, 1992, pp134-14.
0), it is known that this easily occurs when a region in which an impurity having a conductivity type opposite to that of the channel layer is active is present between the elements.

That is, in order to improve the degree of integration, MES
Since the p-layer is formed on the substrate side of the MESFET device in order to suppress the short channel effect that accompanies the miniaturization of the FET device, there has been a problem that the improvement in the degree of integration is hindered.

The present invention has been made in view of the above circumstances, and provides a field effect transistor suitable for integration, which can suppress the short channel effect and simultaneously suppress the inter-element interference due to the side gate effect. With the goal.

[0010]

A field effect transistor according to the present invention is formed inside a substrate including (a) a semi-insulating substrate made of a compound semiconductor and (b) a first region on the surface of the substrate. A channel layer having a first conductivity type; (c) a potential barrier layer having a second conductivity type, which is formed only immediately below the channel layer on the substrate side;
A first heavily doped layer having a first conductivity type and formed inside a substrate including a second region on the surface of the substrate in contact with the region; and (e) a second region sandwiching the first region. A second heavily doped layer having a first conductivity type formed inside the substrate, including a third region of the surface of the substrate opposite to, and (f) formed on the surface of the channel layer. A Schottky electrode, (g) a first ohmic electrode formed on the surface of the first high-concentration doped layer, (h) a second ohmic electrode formed on the surface of the second high-concentration doped layer, It is characterized in that it is configured to include.

Here, the compound semiconductor is GaAs, the first conductivity type is n-type, and the second conductivity type is p-type.
It may be characterized by being a mold.

Further, according to the method of manufacturing a field effect transistor of the present invention, (a) a photoresist film is formed on a substrate except a first region on the surface of a substrate made of a compound semiconductor having a semi-insulating property, and the substrate is formed on the substrate. A first step of implanting first ions for expressing a first conductivity type after implantation at a first reaching depth and a first concentration; and (b) isotropic etching of the photoresist film by a dry etching method. The exposed region of the substrate is a second region that extends the extension of the first region,
And (c) a second ion that expresses the second conductivity type after being injected into the substrate, a second reaching depth shallower than the first reaching depth, and a second concentration higher than the first concentration. And (d) after forming a photoresist film in a region excluding the third region and the fourth region sandwiching the channel formation region in the second region, and A fourth step of implanting a third ion expressing the second conductivity type at a third reaching depth deeper than the first reaching depth and a third concentration higher than the second concentration, and ( e) while forming the first ohmic electrode on the surface of the third region,
Forming a second ohmic electrode on the surface of the fourth region;
The method is characterized by including a fifth step and (f) a sixth step of forming a Schottky electrode on the surface of the channel formation region.

Here, the compound semiconductor may be GaAs, the first conductivity type may be n-type, and the second conductivity type may be p-type. In addition, the first ions may be Be ions, the second ions may be Si ions, and the third ions may be Si ions.

[0014]

Since the field effect transistor of the present invention is constructed as described above, when a voltage is applied between the heavily doped layer of the source and the heavily doped layer of the drain in order to operate this MESFET, The potential barrier layer having a conductivity type different from that of the channel layer formed immediately below the channel layer suppresses the leak current and effectively suppresses the short channel effect. Further, since the potential barrier layer is formed only under the channel layer and there is no portion having the same conductivity type as that of the potential barrier layer outside the element beyond the source portion or the drain portion, the side gate effect is suppressed. , The interference of one operating MESFET device with the operation of another device and the interference of the operation of another device with this MESFET device is reduced.

Further, according to the method of manufacturing a field effect transistor of the present invention, first, ions are implanted into the substrate for the potential barrier layer, and then the pattern of the photoresist used at the time of ion implantation for the potential barrier layer. Is isotropically etched to include a region of the surface of the substrate on which the ion implantation for the potential barrier layer is performed, and the ion implantation is performed from the enlarged region to the substrate for the channel layer. Then, similarly to the conventional manufacturing method, the source, the drain, and the gate are formed in a self-aligned manner. Therefore, the ion-implanted region for the channel layer always oversizes the ion-implanted region for the potential barrier layer, and therefore, beyond the region where the MESFET element is formed,
The MESFET device can be constructed without allowing the portion having the same conductivity type as the potential barrier layer to exist. Further, the ion implantation for the potential barrier layer is set such that the average depth of implantation is set deeper and the ion concentration is set smaller than that of the ion implantation for the channel layer. Is formed.

[0016]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.

FIG. 1 is a block diagram of a field effect transistor according to an embodiment. The field effect transistor is a Schottky junction field effect transistor (MESFET), and includes (a) a substrate 100 having a semi-insulating property made of a GaAs crystal, and (b) a substrate including a surface of a first region on the surface of the substrate 100. The channel layer 300 having n-type conductivity formed therein, and (c) the substrate 1 of the channel layer 300.
00, a potential barrier layer 200 having p-type conductivity formed immediately below, and (d) the substrate 100 in contact with the first region.
Formed inside the substrate including the surface of the second region of the surface of
A heavily doped source layer 410 (source n ⁺ layer) having n-type conductivity and (e) a third region on the surface of the substrate 100, which is located on the opposite side of the second region with the first region interposed therebetween. Drain heavily doped layer 420 (drain n ⁺ layer) having n-type conductivity and formed inside the substrate 100 including the surface
And (f) the Schottky electrode 600 (gate electrode) formed on a part of the surface of the channel layer 300, and (g) the ohmic electrode 510 (source) formed on a part of the surface of the source high-concentration doped layer 410. Electrode) and (h) an ohmic electrode 520 formed on a part of the surface of the drain heavily-doped layer 420. Board 100
An insulating layer is formed between the electrodes on the surface and around the MESFET element.

When operating the above MESFET element, a voltage is applied between the source electrode 510 and the drain electrode 520. As a result of the application of this voltage, an electric field is generated between the source n ⁺ layer 410 and the drain n ⁺ layer 420 inside the substrate 100, and a leak current tends to flow through the substrate side of the channel layer 300. However, the channel layer 300
Since the p-type potential barrier layer 200 is formed immediately below the substrate side, the potential barrier between the n ⁺ layers 410 and 420 is increased, the leak current is suppressed, and the short channel effect is effectively suppressed.

Further, since the p layer is only the potential barrier layer 200 directly below the channel layer 300 and does not exist outside the region of the MESFET device, that is, at the boundary with other devices, it is remarkably expressed through the p layer. The inter-element interference due to the side gate effect is reduced.

The above field effect transistor is manufactured by the following method.

First, a photoresist film 800 is formed on the surface of a substrate 100 made of GaAs crystal having a semi-insulating property, and Be ions are implanted into the substrate 100 at an energy = 70.
Ion implantation is performed with keV and a dose amount of 5 × 10 ¹¹ cm ⁻² (see FIG. 2A).

Next, the photoresist film 800 is isotropically etched by a dry etching method to extend the extension of the exposed region of the substrate. The dry etching conditions at this time are
O ₂ gas is used, flow rate = 60 sccm, pressure = 0.5
torr, RF power = 200 W, etching time = 1
0 minutes, and the photoresist layer 800 is isotropically about 0.
It is retracted by about 5 μm (see FIG. 2B). Continuing,
Implantation energy of Si ions into the substrate 100 = 30 keV,
Ion implantation is performed at a dose amount of 5 × 10 ¹² cm ^-2 (Fig. 2
(See (c)).

Next, plasma CVD is performed on the surface of the substrate 100.
A Si ₃ N ₄ film 810 is deposited by the method. This Si ₃ N
_{The 4th} film 810 is a protective film for the later annealing, and protects the surface of the substrate 100 throughout the entire process of manufacturing the FET, and suppresses variations in device characteristics from process to process. Subsequently, the lowermost photoresist layer 820, the sputter-deposited SiO ₂ layer 830, and the photoresist layer 84.
0s are sequentially formed (see FIG. 2D). Then, after patterning the uppermost photoresist layer 840, CF ₄ +
The sputtered SiO ₂ layer 830 is formed by reactive ion etching (RIE) using H ₂ gas, and R is formed by using O ₂ gas.
The photoresist layer 820 is removed by IE. At this time, the photoresist layer 840 is also removed.

Next, using the remaining SiO ₂ layer 830 / photoresist layer 820 multilayer resist as a mask, Si ion implantation energy = 300 k for forming an n ⁺ layer.
Ion implantation is performed at eV and a dose amount of 5 × 10 ¹³ cm ⁻² (see FIG. 2E). Then, after depositing a SiO ₂ film 850 by sputtering (see FIG. 3A), lift-off is performed,
A heat treatment is performed in an N ₂ atmosphere to activate the p, n, and n ⁺ ion implantation layers (see FIG. 3B).

Next, with respect to the regions above the source n ⁺ layer 410 and the drain n ⁺ layer 420, the SiO ₂ film 850 is removed by reactive ion etching (RIE) and the Si ₃ N ₄ film 810 is removed by plasma etching. Subsequently, an ohmic metal is vapor-deposited to form the source electrode 510.
Then, the drain electrode 520 is formed (see FIG. 3C). Furthermore, after removing the Si ₃ N ₄ film 810 above the channel layer 300 by plasma etching, a Schottky electrode is formed by vapor deposition to form a gate electrode. (Fig. 3 (d)
reference).

In this method of manufacturing a field effect transistor, first, the ion implantation for the potential barrier layer 200 is performed, and then the pattern of the photoresist used in the ion implantation for the potential barrier layer 200 is isotropically etched. After that, ion implantation for the channel layer 300 is performed. Then, similarly to the conventional manufacturing method, the source, the drain, and the gate are formed in a self-aligned manner. Therefore, the ion implantation region for the channel layer 300 must be the potential barrier layer 200.
Oversize the ion implantation area for
A portion having the same conductivity type as the potential barrier layer 200 does not exist beyond the formation region of the ET element, and the MESFET does not exist.
Configure the element. Further, in the ion implantation for the potential barrier layer 200, the average arrival depth of the implantation is set deeper and the ion concentration is set smaller than that of the ion implantation for the channel layer 300. Thus, the potential barrier layer 200 is surely formed.

The present invention is not limited to the above embodiment, but various modifications can be made. For example, MESFET
The necessity of simultaneously suppressing the short channel effect and the side gate effect in (1) is not limited to the case of an integrated circuit using GaAs as a base material, but is also essential in the case of using another compound semiconductor as a base material. In this case as well, the structure of the field effect transistor and the method of manufacturing the field effect transistor of the present invention in which the potential barrier layer is formed only directly below the channel layer are similarly effective.

[0028]

As described above in detail, according to the field-effect transistor of the present invention, since the potential barrier layer having a conductivity type different from that of the channel layer is formed only directly under the channel layer, the short channel effect and the side gate are obtained. It is possible to realize the Schottky junction type field effect transistor element which can effectively suppress the effect and can be integrated.

Further, according to the method for manufacturing a field effect transistor of the present invention, ions are implanted into the substrate for the potential barrier layer, and then the pattern of the photoresist used at the time of ion implantation for the potential barrier layer is formed. Same as the conventional manufacturing method after ion implantation into the substrate for the channel layer from the enlarged region including the surface area of the substrate that isotropically etched and subjected to ion implantation for the potential barrier layer Then, the source, the drain, and the gate are formed in a self-aligned manner. Therefore, the ion implantation region for the channel layer is
Since the ion implantation region for the potential barrier layer is always oversized, a Schottky junction field effect transistor with a reduced side gate effect, in which a portion having the same conductivity type as the potential barrier layer does not exist beyond the device formation region. The element can be configured. At the same time, according to the method for manufacturing a field effect transistor of the present invention, the ion implantation for the potential barrier layer is set to have a deeper average reaching depth and the ion concentration is set to be smaller than that for the channel layer. Therefore, since the potential barrier layer is reliably formed immediately below the channel layer,
A Schottky junction field effect transistor device with reduced short channel effect can be constructed.

[Brief description of drawings]

FIG. 1 is a structural diagram of a field effect transistor according to an embodiment of the present invention.

FIG. 2 is a process drawing of the method for manufacturing the field effect transistor according to the embodiment of the present invention.

FIG. 3 is a process drawing of the method for manufacturing the field effect transistor according to the embodiment of the present invention.

FIG. 4 is a structural diagram of a conventional field effect transistor.

[Explanation of symbols]

100 ... Semi-insulating substrate, 200 ... Potential barrier layer (p layer),
300 ... Channel layer (n layer), 410 ... Source n
⁺ Layer, 420 ... Drain n ⁺ layer, 510 ... Source electrode,
520 ... Drain electrode, 600 ... Gate electrode

Claims (5)

[Claims] 1. A semi-insulating substrate made of a compound semiconductor, a channel layer having a first conductivity type formed inside the substrate including a first region on a surface of the substrate, and the channel layer. A potential barrier layer having a second conductivity type, which is formed only immediately below the substrate side, and is formed inside the substrate including a second region on the surface of the substrate in contact with the first region, A first heavily doped layer having a first conductivity type, and a third region on a surface of the substrate opposite to the second region with the first region sandwiched between the third region and the inside of the substrate. A second heavily doped layer having the first conductivity type, a Schottky electrode formed on the surface of the channel layer, and a first heavily doped layer formed on the surface of the first heavily doped layer. Ohmic electrode, and the second heavily doped The second field effect transistor and the ohmic electrode, characterized in that it is configured to include a formed on the surface of the. 2. The compound semiconductor is GaAs, the first conductivity type is n-type, and the second conductivity type is p-type.
The field effect transistor according to claim 1, wherein the field effect transistor is a type. 3. A photoresist film is formed on a surface of a substrate made of a compound semiconductor having a semi-insulating property except for a first region, and a first conductivity type film is introduced into the substrate to develop a second conductivity type. A first step of implanting ions at a first reaching depth and a first concentration; and isotropically etching the photoresist film by a dry etching method to extend the exposed region of the substrate to the outside of the first region. And a second step of forming a second region in which the second region is expanded, and second ions that develop the first conductivity type after being implanted in the substrate are provided with a second reaching depth shallower than the first reaching depth and A third step of implanting at a second concentration higher than the first concentration, and a photoresist in a region other than the third region and the fourth region sandwiching the channel formation region in the second region. After forming the film, the first A fourth step of implanting third ions expressing a conductivity type at a third reaching depth deeper than the first reaching depth and a third concentration higher than the second concentration; A fifth step of forming a first ohmic electrode on the surface of the third region and a second ohmic electrode on the surface of the fourth region, and a Schottky electrode on the surface of the channel forming region. And a sixth step of forming the field effect transistor. 4. The field effect transistor according to claim 3, wherein the compound semiconductor is GaAs, the first conductivity type is n type, and the second conductivity type is p type. Manufacturing method. 5. The first ion is a Be ion,
4. The method of manufacturing a field effect transistor according to claim 3, wherein the second ions are Si ions and the third ions are Si ions.