JPS63244662A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the electrostatic capacitance between a first conducting layer and a second conducting layer without increasing the plane area of a device by extending the first conducting layer along the vertical wall of a groove formed on an isolation region. CONSTITUTION:The title device is provided with the following: a first insulating layer 3 formed on a semiconductor substrate 1, an element isolation region 2 surrounding the first insulating layer 3, and first conducting layers 7, 9 which are formed on the first insulating layer 3 and extend to a part of the isolation region 2. The first conducting layers 7, 9 extend down to the bottom of a groove 8 along a wall almost vertical to the groove 8 formed in the isolation region 2. At the extending part of the layers 7, 9, too, a second conducting layer 11 is overlapped via the second insulating layer 10. Accordingly, the first conducting layers 7, 9 and the second conducting layer 11 can increase the mutual overlapping area without increasing the area size of a device, so that the electrostatic capacitance is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to semiconductors, and particularly to increasing the electrical capacitance between two conductive layers via an insulating layer.

[Prior Art] FIG. 2 is a schematic cross-sectional view illustrating a conventional semiconductor stirrup. In this figure, a first insulating layer 3 made of silicon oxide is formed on a silicon substrate 1.
The insulating layer 3 is surrounded by an element isolation region 2 made of silicon oxide.

A first conductive layer 4 made of polycrystalline silicon is formed on the first insulating layer 3 by chemical etching using a photoresist mask, and this first conductive layer 4 is formed on the isolation region 2. It has spread to part of the A second insulating layer 5 made of silicon oxide obtained by thermally oxidizing the polycrystalline silicon is layered on the first conductive layer 4, and this second insulation layer 5 is formed by the second conductive layer 6. covered by.

In such a semiconductor device, the first conductor 1! Since the layer 4 faces the second conductive layer 6 via the second insulation 115, these conductive layers can act as capacitors. In this case, the electrical capacitance of the second insulating layer 5 depends on the thickness of the second insulating layer 5, and the first conductive layer 4 and the second conductive layer 6
It depends on the area of the overlapping portion with the insulating layer 5 interposed therebetween. Incidentally, the etching width between the two first conductive layers 4 extending from adjacent device regions separated by the isolation region 2 depends on the processing accuracy of the photoresist mask, and also depends on the processing accuracy of the photoresist mask during chemical etching. Excessive etching downward 13
Depends on 11m. With current technology, the minimum etching width is about 1.0 .mu.-.

[Problems to be solved by the invention] Conventional semiconductor devices are configured as described above.
Therefore, in order to increase the capacitance between the first conductive layer 4 and the second conductive layer 116, the second insulating layer 5 must be made thinner, or these two conductors can be connected via the second insulating layer 5. The area of the overlapping portion of the two conductive layers 4 and 6 must be increased. However, if the second insulation 1i15 is made thinner, the first conductor 'R'
The insulation between M4 and the second conductor 116 is reduced, reducing the reliability of the device. Furthermore, if an attempt is made to increase the area of the overlapping portion of the two conductors 1714 and 6, the planar area of the device will increase, impairing the miniaturization of the device.

The present invention was made to solve such problems, and without reducing the insulation properties of the second insulating layer 5,
Another object of the present invention is to provide a semiconductor device in which the capacitance between two conductive layers 4 and 6 is increased without increasing the area size of the device.

[Means for Solving the Problems] A semiconductor device according to the present invention includes a first insulating layer formed on a semiconductor substrate, an element isolation region surrounding the first insulating layer, and a first insulating layer formed on the first insulating layer. a first conductive layer formed on the isolation region and extending over a portion of the isolation region, the first conductive layer extending along substantially vertical walls of the trench formed on the isolation region. It extends to the bottom and further includes an insulating layer of tE2 extending over the first conductive layer and a second conductive layer covering the second insulating layer.

[Function] The conductive layer Ill in the semiconductor device according to the present invention extends along the almost vertical wall of the trench formed on the isolation region to the bottom of the trench, and the extended portion also follows the line of sight of J1!2. A second conductive layer is stacked with the layer interposed therebetween. Therefore, the area where the first conductive layer and the twelve conductive layers overlap each other can be increased without increasing the area size of the device, that is, the capacitance can be increased.

Embodiment of the Invention FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the invention. In this figure, a first insulating layer 3 made of silicon oxide is formed on a silicon substrate 1, and this insulating layer 3 has two insulating layers 1111 surrounded by an element isolation region 2 made of silicon oxide. On layer 3 is a first layer made of polycrystalline silicon.
A planar portion 7 of the conductive layer is formed, which extends to a part above the separation region 2 .

The planar portion 7 of the first conductive layer is formed by thermally oxidizing the surface of the polycrystalline silicon film formed on the first insulation layer 3 and the isolation region 2, and then selectively chemically etching it using a photoresist mask. obtained by doing. A groove 8 is formed on the isolation region 2 .

This full 8 is formed by selectively chemically etching the planar portion 7 of the first conductive layer and then selectively anisotropically etching the element isolation region 2 without removing the photoresist mask. be able to. Along the substantially vertical walls of this groove 8, a planar portion 71. of the first conductive layer. : Tsunaga 6
A vertical section 9 is formed. The vertical portion 9 of this first conductive layer 9 is connected to the surface of the groove 8 and the 14th m! It can be formed by depositing a polycrystalline silicon film with silicon oxide on the planar portion 7 of i1 and performing anisotropic chemical etching on the entire surface without using a photoresist.

After the planar portion 7 and vertical portion 9 of the first conductive layer 7 are formed, the silicon oxide surface on the planar portion 7 is removed, and then the first conductive layer 7 is formed. By simultaneously thermally oxidizing the flat part 7 and the vertical part 9 of JIM, the first conductive 1
A second insulator 1li10 made of silicon oxide is formed on the surface of i17.9. This second insulating layer 10 is covered by a second conductive layer 11.

In the device formed in this way, the thickness of the isolation region 2 is 1°0 μm, the depth of the groove 8 is 0625 μm, and the film thickness of the first conductive layer 7.9 is @0.3 μm J=t. , 2nd termination #M10 (7) Jut-0.05μm,! =shi, 1st
Assuming that the horizontal length of the flat portion 7 of the conductor 1m is 3 μm, and the width of the first conductor 1tH17,9 in the depth direction in FIG. 1 layer 17
Toga 211th! The area of the overlapping portion via the edge layer 7o increases by about 13% compared to the conventional device. An increase in the area of this rounded portion directly results in an increase in the capacitance between the first sis 7.9 and the second conductive layer 11. In addition, separation area 2
By making the groove 8 thicker and forming the groove 8 deeper, the capacitance between the first conductor 1117.9 and the second conductor layer 11 can be further increased without increasing the planar area of the device. can be increased. Further, in the structure according to the dimension example of the above-described embodiment, the chemical etching depth between the flat 1i1i portions 7 of the first conductive layer that are adjacent to each other on the 111 m area is approximately 1.0 m.
The vertical portion 9 of the first conductive layer can be formed sufficiently even with μ error, and the second conductor 11811 can be formed without causing disconnection.

In the above-mentioned example, the groove 8 is formed by chemical etching in the isolation region 2 that has already been formed. It will be understood that the trench may be oxidized to form the M region.

Further, after depositing polycrystalline silicon acid and thermally oxidizing its surface, the planar portion 7 of the first conductive layer was formed by selective chemical etching using a photoresist mask.
! ! It will be understood that a silicon oxide film or a silicon nitride film may be formed by chemical vapor deposition instead of chemical vapor deposition. Furthermore, when forming the vertical portion 9 of the first conductive layer by anisotropic chemical etching of polycrystalline silicon acid, if this etching is performed with high precision, the silicon on the planar portion 7 of the first conductive layer described above can be The oxide or silicon nitride film can be omitted.

[Effects of the Invention] As described above, according to the present invention, the first conductive layer can be expanded along the vertical walls of the groove formed on the isolation region, so that the planar area of the device can be increased. Therefore, it is possible to provide a semiconductor device in which the capacitance between the first conductive layer and the second s1 layer is increased.

[Brief explanation of drawings]

FIG. 1 is according to one embodiment of the present invention! FIG. 3 is a schematic cross-sectional view illustrating an r-conductor device. FIG. 2 is a sectional view showing a conventional semiconductor device. In the figure, 1 is a silicon substrate, 2 is an isolation region made of silicon oxide, 3 is a first insulating layer made of silicon oxide, 4 is a first conductive layer made of polycrystalline silicon, and 5 is made of silicon oxide. 6 is a second conductive layer; 7 is a planar portion of the *i conductive layer made of polycrystalline silicon; 8 is a groove; 9 is a vertical portion of the first conductive layer made of polycrystalline silicon; 10 11 represents a second insulating layer made of silicon oxide, and 11 represents a second conductive layer. In addition, in each figure, the same reference numerals indicate the same or corresponding parts.

Claims (5)

[Claims] (1) A semiconductor substrate, a first insulating layer formed on the substrate, an element isolation region surrounding the first insulating layer, and an element isolation region formed on the first insulating layer and above the isolation region. a first conductive layer extending to a part of the first conductive layer;
a conductive layer extending along substantially vertical walls of the trench formed on the isolation region to the bottom of the trench, further comprising: a second insulating layer overlapping the first conductive layer; A semiconductor device comprising: a second conductive layer covering the second insulating layer. (2) The semiconductor device according to claim 1, wherein the first conductive layer is polycrystalline silicon, and the second insulating layer is silicon oxide. (3) The semiconductor device according to claim 1 or 2, wherein the substrate is silicon and the first insulating layer is silicon oxide. (4) The semiconductor device according to any one of claims 1 to 3, wherein the isolation region is made of silicon oxide. (5) The semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is a memory device.