JPS60225461A - Manufacture of semiconductor ram device - Google Patents

Abstract

PURPOSE:To obtain MOS dynamic memory elements of large capacitance per unit area which are suitable for increase in integration by a method wherein a groove is dug in a field oxide film and filled with a capacitor made of poly Si-dielectric-poly Si. CONSTITUTION:A field oxide film of 0.8-1.5mum in thickness is formed on a P type Si semiconductor substrate 1 by thermal oxidation. Next, the groove 7 to be filled with the capacitor is formed in the field oxide film 6, and the depth of the groove 7 is made equal to the thickness of the oxide film 6. At the bottom of the groove 7, an oxide film 9 of 300-1,000Angstrom in thickness is formed by thermal oxidation. This first poly Si layer 11 containing a high concentration of phosphorus (P) is deposited to a film thickness of 1,500-2,000Angstrom . Furthar, an Si nitride film 13 is deposited to a film thickness of 200-400Angstrom as the dielectric. The second poly Si layer 14 is deposited thereon to a film thickness of 1,500- 2,000Angstrom , thus filling up the groove 7, resulting in the formation of the capacitor. Therefore, the titled device can be utilized as a super-high integrated memory by increasing the capacitance per unit area.

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to a method for manufacturing a semiconductor RAM device, and more specifically, to a 1-transistor, 1-carrier/q-shita type MI that can be highly integrated.
The present invention relates to a method of manufacturing an S dynamic memory element.

(Conventional technology) Conventionally, M
Widely used in O3 random access memory (RAM). Recently, 256-bit DRAMs have also been put into practical use, and efforts are being made to further increase the degree of integration to 1M bits.

However, the following problems arise in achieving this high degree of integration. In other words, as the area of a capacitor decreases with higher integration, a single transistor is used to store information by storing charge in the capacitor.

In a single-canon transistor type MOS dynamic memory, it is difficult to secure a margin against alpha rays and noise.

Therefore, as a method to increase the capacitance per unit area of the capacitor, attempts have been made to thin 5i02, which is the dielectric material of the capacitor, and to use a high dielectric material. There are problems with electrical characteristics such as leakage of the dielectric film and breakdown voltage, making it impractical.

υ Also, attempts have been made to increase the capacitance of a capacitor by digging a trench in a semiconductor substrate and using the side surface of the trench as a capacitor. This is 1982 IEEE International
tional Electron Davises M
eating.

26, 9 P, P, 806-808 and Nikkei Electronics 1982.12-20P, P, 74-75. There are drawbacks such as the inability to monitor

(Objective of the Invention) The object of the invention is to provide a method for manufacturing a semiconductor RAM device that can obtain a high-yield MIS dynamic memory element that has a large capacitance per unit area and is suitable for high integration. It's about doing.

(Structure of the Invention) The present invention includes a step of forming a field oxide film on a semiconductor substrate, a step of forming a trench reaching the substrate in the field oxide film, and a step of forming an oxide film at the bottom of the formed trench. a first polysilicon layer on the inner surface of the groove;
A semiconductor RA comprising the step of sequentially stacking a dielectric layer and a second polysilicon layer to form a capacitor.
It is in the manufacturing method of the M device.

(Example) A cross-sectional view of the manufacturing process of an example of the present invention is shown in Figures 1-(J).
Shown below. The explanation will be given below with reference to this figure.

First, a film with a thickness of 300 to 50 mm is coated on a P-type silicon semiconductor substrate 1.
A silicon oxide film 2 of 0x is formed by thermal oxidation, and a silicon nitride film 3 of 1500 to 2500x is deposited thereon by CVD (chemical vapor deposition). A resist 4 is selectively formed on the silicon nitride film 3 at a location that will become an active region, and the silicon nitride film 3 is etched using a dry etching device using CF4 and 02.

After that, using the resist 4 and the silicon nitride film 3 as a mask, ? The channel stozzo layer 5 was formed by ion-implanting Ron (B) at an energy of 50 to 100 keV and a dose of 1 to 3 x 1013 cm-2.
The structure is shown in 4).

The resist 4 is removed and a field oxide film 6 having a thickness of 0.8 to 1.5 μm is formed by thermal oxidation in a wet oxygen atmosphere using the silicon nitride film 3 as an oxidation-resistant mask. Thereafter, the silicon nitride film 3 and the rad oxide film 2 are removed to obtain the structure shown in FIG. 1(B).

Next, there is a carrier A in the field oxide film 6? A groove 7 having an opening of, for example, 1 m x 4+11 is formed for embedding the groove. This selectively forms resist 8 and C
Etching is performed using an anisotropic dry etching device using HF3 and C2F6 gases so as to have a vertical cross-sectional shape. Since the etching speed of the field oxide film 6 is about 10 times faster than that of silicon, the silicon substrate 1 can be used as an etching stopper, and the depth of the groove 7 can be made equal to the thickness of the field oxide film. It's easy to do. [FIG. 1 (C5)] After removing the resist 8, the bottom of the trench 7 and the exposed portion of the silicon substrate 1 in the active region are oxidized by thermal oxidation to form an oxide film 9 with a thickness of 300 to 1000×. , a part of the oxide film on the active region is removed using photolithography technology, and an opening 10 is provided. A first silicon layer 11 containing a concentration of 020 cm-3 is deposited to a thickness of 1500 to 2000X, and e) I
By J Sogerafy technology No? Turn. Note that the N+ diffusion layer 12 is formed during the deposition of the first pre-silicon layer 11 and during the subsequent heat treatment process.

[Figure 1 (G)] Furthermore, the silicon nitride film 13 is deposited as a dielectric by low pressure CVD.
A second polysilicon layer 14 is similarly deposited thereon to a thickness of 1500 to 2000X using a low pressure CVD method to completely fill the trench 7.

A resist 15 is selectively formed on the second polysilicon layer 14, and the second polysilicon layer 14 and silicon nitride film 13 are etched using a dry etching device using CF4 and 02 gases using the resist 15 as a mask. .

[FIG. 1(F)] After removing the resist 15, an oxide film 16, which will become a dirt oxide film of the transfer transistor, is formed on the exposed silicon substrate 1 by thermal oxidation, and at the same time, the first I silicon layer 11 is deposited on the exposed silicon substrate 1. An oxide film 16 is also formed on the second polysilicon layer 14 for interlayer insulation. Molybdenum silicide (Mo5i2) is deposited on this oxide film 16 by sputtering.
A resist 18 is selectively formed on the molybdenum silicide 12. [FIG. 1(G)] Using this resist 18 as a mask, the molybdenum silicide 12 and oxide film 16 are etched using a dry etching device using CF4 and 02 gases. After removing the regimen, molybdenum silicide 17. Second polysilicon layer 14. Using the first I silicon layer 11 as a mask, arsenic (As) is ion-implanted at an energy of 40 to 60 keV and a dose of 5 x 10 to 2 x 10" cm-2 to form N1.
Diffusion layers 19 and 20 are formed. [Figure 1 (b)] Furthermore, an insulating film 21, for example, phosphor glass (PSG) is deposited on the entire surface, a contact hole 22 is opened on the diffusion layer 20, and a pit line 23 is formed with aluminum (HT). do. [FIG. 1(1)] Finally, a protective film 24 is formed on the entire surface to complete the semiconductor RAM device. [Fig. 1 (J)] A top view of Fig. 1 (, T) is shown in Fig. 2.

In the embodiment described above, a method of manufacturing an N-channel MOS cell using a P-type silicon semiconductor substrate was shown, but if an N-type silicon semiconductor substrate is used and the polarity of the doped impurity is reversed accordingly, a P-channel MOS cell can be produced. Needless to say, it is possible to do so. Further, it is also possible to provide a well region in the substrate and make it CMO8. moreover,
Although silicon nitride was used as the dielectric in this embodiment, a silicon oxide film or the like may also be used.

(Effects of the Invention) As explained above, a trench is dug in the field oxide film, and the trench is made up of polysilicon, dielectric material, and polysilicon. Since the capacitors are buried in capacitors/v, the capacitance of capacitors/4' per unit area can be increased and can be used as an ultra-highly integrated memory. Furthermore, since the capacitor is not a MOS capacitor but is made of polysilicon-dielectric-polysilicon, there are the following advantages. First, the method of forming a MOS capacitor by digging a trench in a silicon substrate and forming an oxide film on the sides and bottom of the trench does not provide an oxide film with good dielectric strength due to damage and stress during etching. Since such an oxide film is not used as the capacitor, the withstand voltage of the xeno capacitor is good. Second, in order to reduce the influence of power supply voltage fluctuations during operation, it is desirable to set one side of the capacitor to v8B potential (usually ground potential), but this is not necessary in the case of a MOS capacitor/4' capacitor. Third, since the capacitor is surrounded by an oxide film and insulated from the substrate, carriers generated in the substrate due to alpha rays or impact ionization will not flow into the capacitor and cause malfunction.

Also, when digging trenches, as an advantage on the manufacturing process.

In-line monitoring is possible without using the board as a stock/e-.

That is, since the trench is formed with the same depth as the field oxide film thickness, the trench depth can be monitored using the field oxide film thickness, and the field oxide film thickness can usually be easily controlled. - The reproducibility of depth is good.

Furthermore, according to the present invention, the capacity of the canopy is 4
There is an advantage that it is possible to easily obtain 0 to 50 fF (l fF - 10 F) or more.

[Brief explanation of drawings]

Figures 1 to 1J are cross-sectional views of steps in an embodiment of the present invention. FIG. 2 is a top view of FIG. 1 (7). 1... P-type silicon semiconductor substrate, 2... Pad silicon oxide film, 3... Silicon nitride film, 418g15e
18... Resist, 5... Channel resist layer, 6... Field oxide film, 7... Groove, 9.16
... Oxide film, 10... Opening, 11... First silicon layer, 12°19.20... N+ diffusion layer, 13
... silicon nitride oxide film, 14 ... second polysilicon layer, 17 ... molybdenum silicide, 21 ... insulating film, 22 ... contact hole, 23 ... bit line, 24 ... Protective film. Patent Applicant: Oki Electric Industry Co., Ltd. Agent Toshiaki Suzuki Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 0 7 19 16 Figure 2 1917 1. Indication of the Case 1981 Patent Application No. 081170 2 Invention Name: Manufacturing method of semiconductor RAM device 3, relationship with the amended case Patent applicant address (〒105) 1-7-12 Toranomon, Minato-ku, Tokyo
No. Oki Electric Industry Co., Ltd. Name (6892) Patent Attorney Toshiaki Suzuki Drawing "Figure 1 (J) J 6. Contents of amendments Attachment 6. Contents of amendments (1) Line 4 of page 5 of the specification ``r1wMX4 nod'' is corrected to ``r1ts x 4μm''. (2) In the 10th line of page 9 of the same book, the phrase ``In this case, it becomes unnecessary. Figure (J)” should be corrected as shown in the attached sheet.

Claims (1)

[Claims] forming a field oxide film on a semiconductor substrate; forming a trench in the field oxide film reaching the substrate; forming an oxide film at the bottom of the formed trench;
A method for manufacturing a semiconductor RAM device, comprising the step of: thereafter, sequentially stacking a first polysilicon layer, a dielectric layer, and a second polysilicon layer on the inner surface of the groove to form a cap.