JPS63229376A - Level detection circuit - Google Patents

Level detection circuit

Info

Publication number
JPS63229376A
JPS63229376A JP6315587A JP6315587A JPS63229376A JP S63229376 A JPS63229376 A JP S63229376A JP 6315587 A JP6315587 A JP 6315587A JP 6315587 A JP6315587 A JP 6315587A JP S63229376 A JPS63229376 A JP S63229376A
Authority
JP
Japan
Prior art keywords
terminal
voltage
output
counter
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6315587A
Other languages
Japanese (ja)
Other versions
JPH0646198B2 (en
Inventor
Masashi Sato
佐藤 政司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ando Electric Co Ltd
Original Assignee
Ando Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ando Electric Co Ltd filed Critical Ando Electric Co Ltd
Priority to JP62063155A priority Critical patent/JPH0646198B2/en
Publication of JPS63229376A publication Critical patent/JPS63229376A/en
Publication of JPH0646198B2 publication Critical patent/JPH0646198B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To set an input voltage to a reference voltage, by detecting positive and negative components of AC voltage overlapping the input voltage to adjust the input voltage so that both the components equal. CONSTITUTION:A voltage V is applied to one end of a comparator 1 at an input terminal 7 while a voltage V0 as reference voltage 2 to be other end thereof. An output of the comparator 1 is applied to a D terminal of a flip-flop FF3 while an output pulse of a pulse generator 4 to a T terminal. The output pulse is also applied to a T terminal of counters 5a and 5b. A '1' terminal output of the FF3 enters a CE terminal of the counter 5a while a '0' terminal output does a CE terminal of the counter 5b. A decision device 6 judges the size of outputs of the counters 5a and 5b to vary an input voltage V so that they equal. Thus, the input voltage V can be set accurately to a reference voltage V0.

Description

【発明の詳細な説明】 (a)発明の技術分野 この発明は、入力電圧を基準電圧と等しくなるように調
節する場合に、入力電圧に@畳している波形の影響が少
なくなるようにしたレベル検出回路についてのものであ
る。
Detailed Description of the Invention (a) Technical Field of the Invention The present invention reduces the influence of a waveform superimposed on the input voltage when adjusting the input voltage to be equal to a reference voltage. This is about the level detection circuit.

(bl従来技術と問題点 ! ?Jlに、従来技術によるレベル検出回路を第2図
に示す。
(BL Prior Art and Problems! ?Jl) A level detection circuit according to the prior art is shown in Fig. 2.

第2図の11と12は基準電圧、13と14は比較器、
15はゲート、16は入力端子、17は出力端子である
11 and 12 in Fig. 2 are reference voltages, 13 and 14 are comparators,
15 is a gate, 16 is an input terminal, and 17 is an output terminal.

第2図は、入力端子16に加えられる入力電圧■が基準
電圧11と基準電圧12の間にあるかどうかを判別する
回路を示す。
FIG. 2 shows a circuit that determines whether the input voltage (2) applied to the input terminal 16 is between the reference voltage 11 and the reference voltage 12.

基準電圧11の電圧をVO−Δv1基準電圧12の電圧
をVo+ΔVとすれば、 (Vo+Δv)>V> (Vo−ΔV)のとき、出力端
子17から出力が出て、入力電圧Vが基準電圧Voの範
囲に設定されたことになる。
If the voltage of the reference voltage 11 is VO-Δv1 and the voltage of the reference voltage 12 is Vo+ΔV, when (Vo+Δv)>V> (Vo-ΔV), an output is output from the output terminal 17 and the input voltage V becomes the reference voltage Vo. This means that it is set within the range of .

第2図のVo=2ボルト、Δv=0.5mV程度の電圧
に入力電圧Vを設定する場合がある。
In some cases, the input voltage V is set to a voltage of about Vo=2 volts and Δv=0.5 mV in FIG. 2.

例えば、演算増幅器を光重力測定器の入力に保用した場
合、光入力がない場合の演算増幅器のオフセノト電圧を
設定する。
For example, when an operational amplifier is used as the input of an optical gravity measuring instrument, the offset voltage of the operational amplifier when there is no optical input is set.

第2図のような回路では、電源に交流′電源のリップル
電圧が重畳すると、入力電圧Vを正確に基準、[圧11
と基準電圧12の間に設定することができないという問
題がある。
In the circuit shown in Fig. 2, when the ripple voltage of the AC power supply is superimposed on the power supply, the input voltage V is accurately referenced and the voltage 11
There is a problem that the voltage cannot be set between the reference voltage 12 and the reference voltage 12.

(c)発明の目的 この発明は、入力電圧Vに重畳している交流成分の正の
成分と負の成分をカウントできる回路を提供し、正の成
分と負の成分が等しくなるようにして、入力電圧に重畳
している交流成分の影響を受けない状態で入力電圧Vを
基準電圧に設定できるようにしたレベル検出回路の提供
を目的とする。
(c) Purpose of the Invention The present invention provides a circuit that can count the positive and negative components of the alternating current component superimposed on the input voltage V, so that the positive and negative components are equal. An object of the present invention is to provide a level detection circuit that can set an input voltage V to a reference voltage without being affected by alternating current components superimposed on the input voltage.

(d)発明の実施例 次に、この発明による実施例の構成図を第1図に示す。(d) Examples of the invention Next, a block diagram of an embodiment according to the present invention is shown in FIG.

第1図の1は比較器、2は基準電圧、3はフリ、プフ口
、プ(以下、FFという。)、4はパルス発生器、5a
と5bはカウンタ、6は判定器、7は入力端子、8は出
力端子である。
In Fig. 1, 1 is a comparator, 2 is a reference voltage, 3 is a FF (hereinafter referred to as FF), 4 is a pulse generator, 5a
and 5b are counters, 6 is a determiner, 7 is an input terminal, and 8 is an output terminal.

比較器1の一端には入力端子7の電圧■を加え、比較器
1の他端には基準電圧2の電圧Voを加える。
The voltage ■ of the input terminal 7 is applied to one end of the comparator 1, and the voltage Vo of the reference voltage 2 is applied to the other end of the comparator 1.

FF3のD端子には比較器1の出力を加え、FF3のT
端子にはパルス発生器4の出力パルスを加える。
The output of comparator 1 is added to the D terminal of FF3, and the T
The output pulse of the pulse generator 4 is applied to the terminal.

パルス発生器4の出力パルスは、FF3のTi子のほか
、カウンタ5aのT端子とカウンタ5bのT端子にも加
えられる。
The output pulse of the pulse generator 4 is applied to the T terminal of the counter 5a and the T terminal of the counter 5b as well as to the Ti terminal of the FF 3.

FF3の「1」端子出力はカウンタ5aのCE端子に入
り、FF3の「0」端子出力はカウンタ5bのCE端子
に入る。
The "1" terminal output of FF3 enters the CE terminal of the counter 5a, and the "0" terminal output of FF3 enters the CE terminal of the counter 5b.

判定器6はカウンタ5aの出力とカウンタ5bの出力の
大小を判定する。
The determiner 6 determines the magnitude of the output of the counter 5a and the output of the counter 5b.

次に、第1図の作用を第3図の波形図を参照して説明す
る。
Next, the operation of FIG. 1 will be explained with reference to the waveform diagram of FIG. 3.

第3図(ア)は、入力電圧V1基準電圧vO及び交流電
圧Eの関係説明図である。
FIG. 3(A) is an explanatory diagram of the relationship between the input voltage V1 reference voltage vO and the AC voltage E.

交流電圧Eの周期は20m5とする。The period of AC voltage E is assumed to be 20 m5.

交流電圧Eは入力電圧Vに重畳しているが、基準電圧V
oに対しては、時間TIと時間T2の間は正、時間T2
と時間T3の間は負になっている。
The AC voltage E is superimposed on the input voltage V, but the reference voltage V
For o, the time between time TI and time T2 is positive, time T2
It is negative between and time T3.

第3図(イ)は、パルス発生器4の出力パルス波形図で
あり、パルスの繰返し周期は第3図(ア)の交流電圧E
の周期に比べ、十分短いものを使用する。
FIG. 3(a) is a diagram of the output pulse waveform of the pulse generator 4, and the pulse repetition period is the AC voltage E in FIG. 3(a).
Use one that is sufficiently short compared to the period of .

第3図(つ)は比較器1の出力波形図であり、第3図(
1)はFF3の「1」端子出力である。また、第3図(
オ)はカウンタ5aのカウント値である。
Figure 3 (1) is an output waveform diagram of comparator 1;
1) is the "1" terminal output of FF3. Also, Figure 3 (
E) is the count value of the counter 5a.

第3図(I)の立上りは第3図(イ)のクロックのqト
りと同期し、第3図(1)は第3図(イ)のクロックの
■下りと同期する。
The rising edge of FIG. 3(I) is synchronized with the q rising of the clock in FIG. 3(a), and the rising edge of FIG. 3(1) is synchronized with the falling edge of the clock in FIG. 3(a).

第3図(力)はFF3の「0」端子出力であり、第3図
(キ)はカウンタ5bのカウント値である。
FIG. 3 (force) shows the "0" terminal output of the FF3, and FIG. 3 (g) shows the count value of the counter 5b.

第3図(ア)の交流電圧Eに対応して、第3図(イ)の
パルスは20個のパルスを出している。
Corresponding to the AC voltage E in FIG. 3(a), 20 pulses are output in FIG. 3(b).

第3図(オ)のカウンタ5aのカウント値は13であり
、第3図(キ)のカウンタ5bのカウント値は7である
。これから、交流電圧Eが基準電圧VOに対しては、ア
ンバランスの状態であることがわかり、入力電圧Vをカ
ウンタ5aのカウント値とカウンタ5bのカウント値が
等しくなるまで変化させる。
The count value of the counter 5a in FIG. 3(E) is 13, and the count value of the counter 5b in FIG. 3(G) is 7. From this, it can be seen that the AC voltage E is unbalanced with respect to the reference voltage VO, and the input voltage V is changed until the count value of the counter 5a and the count value of the counter 5b become equal.

カウンタ5aのカウント値とカウンタ5bのカウント値
が等しくなれば、入力電圧Vが基準電圧VOに設定され
たことになる。
When the count value of the counter 5a and the count value of the counter 5b become equal, it means that the input voltage V is set to the reference voltage VO.

m発明の効果 この発明によれば、入力電圧と基準電圧を比較する比較
器と、比較器出力を入力とするFFと、FFの「1」出
力をカウントする第1のカウンタと、FFの「0」出力
をカウントする第2のカウンタとを採用し、入力電圧に
重畳している交流電圧の正の成分と負の成分を検出し、
正の成分と負の成分が等しくなるように入力電圧を調節
するので、入力端子を正確に基準電圧に設定することが
できる。
According to the present invention, a comparator that compares an input voltage with a reference voltage, an FF that receives the output of the comparator as an input, a first counter that counts the "1" output of the FF, and a "1" output of the FF. 0'' output, and detects the positive component and negative component of the AC voltage superimposed on the input voltage,
Since the input voltage is adjusted so that the positive and negative components are equal, the input terminal can be accurately set to the reference voltage.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明による実施例の構成図、第2図は従来
技術による構成図、 第3図は第1図の波形図。 1・・・・・・比較器、2・・・・・・基準電圧、3・
・・・・・フ’J ソプフロノプ(FF)、4・・・・
・・パルス発生器、5a・・・・・・カウンタ、5b・
・・・・・カウンタ、6・・・・・・判定器、7・・・
・・・入力端子、8・・・・・・出力端子、11・・・
・・・基準電圧、12・・・・・・基準電圧、13・・
・・・・比較器、14・・・・・・比較器、15・・・
・・・ゲート、16・・・・・・入力端子、17・・・
・・・出力端子。 代理人  弁理士  小 俣 欽 司 第   1   図 判定器 第2図 は〕咬滞
FIG. 1 is a block diagram of an embodiment according to the present invention, FIG. 2 is a block diagram of a conventional technique, and FIG. 3 is a waveform diagram of FIG. 1. 1...Comparator, 2...Reference voltage, 3.
...F'J Sopfronop (FF), 4...
...Pulse generator, 5a... Counter, 5b.
...Counter, 6...Judgment device, 7...
...Input terminal, 8...Output terminal, 11...
...Reference voltage, 12...Reference voltage, 13...
...Comparator, 14...Comparator, 15...
...Gate, 16...Input terminal, 17...
...Output terminal. Agent Patent Attorney Kin Tsukasa Omata 1st Diagram Judgment Diagram 2 is] occlusion

Claims (1)

【特許請求の範囲】 1 入力電圧と基準電圧を入力とする比較器と、前記比
較器出力をD端子入力とするフリップフロップと、 前記フリップフロップの「1」端子出力を入力とする第
1のカウンタと、 前記フリップフロップの「0」端子出力を入力とする第
2のカウンタと、 クロックパルスを前記フリップフロップのT端子、第1
のカウンタのT端子及び第2のカウンタのT端子に供給
するパルス発生器と、 第1のカウンタ出力と第2のカウンタ出力の大小を判定
する判定器とを備えることを特徴とするレベル検出回路
[Claims] 1. A comparator that receives an input voltage and a reference voltage as inputs, a flip-flop that uses the output of the comparator as a D terminal input, and a first comparator that uses the "1" terminal output of the flip-flop as an input. a second counter that receives the "0" terminal output of the flip-flop; and a second counter that receives the clock pulse from the T terminal of the flip-flop;
A level detection circuit comprising: a pulse generator that supplies the T terminal of the counter and the T terminal of the second counter; and a determiner that determines the magnitude of the first counter output and the second counter output. .
JP62063155A 1987-03-18 1987-03-18 Level detection circuit Expired - Lifetime JPH0646198B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62063155A JPH0646198B2 (en) 1987-03-18 1987-03-18 Level detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62063155A JPH0646198B2 (en) 1987-03-18 1987-03-18 Level detection circuit

Publications (2)

Publication Number Publication Date
JPS63229376A true JPS63229376A (en) 1988-09-26
JPH0646198B2 JPH0646198B2 (en) 1994-06-15

Family

ID=13221058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62063155A Expired - Lifetime JPH0646198B2 (en) 1987-03-18 1987-03-18 Level detection circuit

Country Status (1)

Country Link
JP (1) JPH0646198B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100825762B1 (en) * 2006-08-07 2008-04-29 한국전자통신연구원 Circuit for measuring a discontinuous metal-insulator transitionMIT continuously and MIT sensor using the same circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5796269A (en) * 1980-12-08 1982-06-15 Nec Home Electronics Ltd Pulse signal measurement device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5796269A (en) * 1980-12-08 1982-06-15 Nec Home Electronics Ltd Pulse signal measurement device

Also Published As

Publication number Publication date
JPH0646198B2 (en) 1994-06-15

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