JPH0136142Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a detection device that detects the output frequency of a high frequency inverter, and is accurate and highly accurate even at low output when controlling the power and voltage to be constant intermittently. The present invention aims to provide a detection device capable of detecting an output frequency.

A high frequency inverter is generally used as a power source for heating various steel materials. When heating a member to be heated using such a high frequency inverter, it is well known that power is intermittently supplied to a load to perform predetermined constant power control and further constant voltage control. The problem with such a method is that, for example, in the case of a self-limiting method in which the frequency supplied to the load tank circuit is detected and the main elements of the inverter main circuit are gate-driven based on this detection signal, at the time of resistive output, Not only does the power suspension period (no-voltage period) that is applied to the load become long, the frequency meter needle wanders and the desired frequency cannot be detected accurately, but the main element group is gate driven based on the frequency detection signal. Therefore, it becomes difficult to carry out predetermined control especially at low output, and the operating range of the inverter itself and the inverter is also limited.

The present invention has been devised in view of this point, and will be described in detail below based on the specific circuit configuration of the detection device shown in FIG.

In the same embodiment, 1 is a single inverter formed by pure bridge connection of thyristors, and furthermore, a high frequency inverter that performs predetermined time-division control using multiple sets of single inverters, and 2 is a high-frequency inverter formed by a tuning capacitor C and a reactor L. In the tank circuit, 3 is a detection current generator that takes out the inverter output current, 4 is a voltage detection transformer that takes out the voltage between the terminals of the tank circuit,
5 and 7 are comparators that take out the negative half wave of the output voltage and the negative half wave of the output current, 6 is a monomulti, 8 is a NOT gate, 9 is an R-S type flip-flop, and 10 is a It is an integrating circuit that integrates the output of the monomulti for a predetermined period, 11 is an electronic switch that controls opening/closing of the feedback circuit of the integrating circuit, and 12 is a frequency meter that inputs a DC level voltage signal to indicate the frequency.

The operation of this embodiment configured as described above is explained in the second section.
To explain in detail based on the time chart shown in the figure, since the high frequency inverter intermittently supplies power to the load as shown by the shaded area in Figure 2A, the tank circuit 2 of the load is A current flows that decays over time as shown in the figure. This steady state load current is taken out by current transformer 3, and only the half-wave period of the negative wave of this detected current (shown in Fig. 2D) is taken out by comparator 7 as shown in Fig. 2E. This load detection signal E is NOT
The output of the NOT gate 8 is input to the set input terminal S of the flip-flop 9.
In parallel with this operation, the voltage between the terminals of the tank circuit 2 is taken out by the transformer 4, and only the half-wave period of the negative wave of this detected voltage A (the shaded part in Fig. 2A) is detected by the comparator 5 as shown in Fig. 2B. The negative wave detection signal B is inputted into a monomultiplier of 6 to obtain a signal C as shown in FIG. 2C having a predetermined width from the rising edge of the B signal. This C signal 10 is input to an integrating circuit for predetermined integration. When the integrating circuit 10 is in operation, the output of the NOT gate 8 is input to the set input terminal S of the flip-flop 9, and Since the output signal B of the comparator 5 is input to the reset input terminal R, when each comparator 5 and 7 detects a half-wave period of the negative wave of the voltage and current, the B signal is input to the reset terminal R, while the B signal is input to the set terminal S. The zero outputs of the NOT gates are respectively input, and the set output signal F (shown in FIG. 2F) is guided from the flip-flop 9 to the electronic switch 11, and the contact of the electronic switch 11 is switched to the 2 side. On the contrary, when the voltage and current pass through the zero point and move into the positive half-wave region, the output signals B and E of each comparator 5 and 7 become zero, the flip-flop 9 is set, and the level of the F signal becomes "1"
Therefore, the contact point of the electronic switch 11 is switched to the 3 side. Therefore, when the detected voltage and detected current are in the half-wave period of the negative wave, the electronic switch 11 is switched to the contact 2 side, and the output signal C of the monomulti 6 is integrated by the integrating circuit 11, and the integrated DC level is A predetermined measurement is performed by inputting the G signal to the frequency meter 12. On the other hand, when the detection voltage and detection current shift to a positive half-wave period, the C signal of the monomulti 6 becomes zero, and the contact of the electronic switch 11 is switched to the 3 side, so that the negative half-wave period The voltage charged in , that is, the G signal to be measured is held as is in the integrating circuit 10 . FIG. 2G shows the operation mode of the integrating circuit 10 during such an operation.
As is clear from FIG. The voltage period and the half-wave period of the positive wave of the supplied power hold the signals to be measured that are charged during the half-wave period of the negative wave, respectively. Therefore, even if the power supplied to the load is intermittent and the no-voltage period becomes long, as occurs when the output is low, the frequency is detected only during the specified measurement period, and the measured value itself is used during the no-voltage period. Therefore, the frequency can be detected accurately and with high precision without causing the pointer of the frequency meter 12 to wobble. Furthermore, according to the present invention, since the frequency at low output is detected with high precision, stable operation can be performed even during self-limiting control that gate drives the main element group based on the detected frequency signal. This has the effect of expanding the range of motion. In this embodiment, the frequency may be detected only during the half-wave period of the negative wave.

[Brief explanation of drawings]

FIG. 1 is a detailed block diagram of a frequency detection device showing an embodiment of the present invention, and FIG. 2 is a time chart showing its operation. 1 is a high frequency inverter, 2 is a tank circuit, 5,
7 is comparator, 6 is mono multi, 8 is NOT
9 is a flip-flop, 10 is an integrating circuit, 11 is an electronic switch, and 12 is a frequency meter.

Claims (1)

[Scope of utility model registration request] An inverter that intermittently supplies power having alternating positive wave half-wave periods and negative wave half-wave periods to a tank circuit of a load, and the output frequency of this inverter is detected. , a first comparator that detects a voltage during a half-wave period of a positive wave or a negative wave, a second comparator that detects a current during a half-wave period of a positive wave or a negative wave, and an output signal of the first comparator. a monomulti that operates and outputs a signal of a predetermined width; an integration circuit that integrates the output signal of the monomulti and uses the integrated output value as a frequency detection signal; and an output signal of the first comparator that is reset by the output signal of the first comparator. and a flip-flop which is set by the output signal of the second comparator and holds the integrated output value of the integrating circuit over the non-voltage period of the inverter output voltage and the non-detection period of the first and second comparators. An output frequency detection device for a high frequency inverter, comprising: