JPH0145273Y2 - - Google Patents

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Publication number
JPH0145273Y2
JPH0145273Y2 JP1382783U JP1382783U JPH0145273Y2 JP H0145273 Y2 JPH0145273 Y2 JP H0145273Y2 JP 1382783 U JP1382783 U JP 1382783U JP 1382783 U JP1382783 U JP 1382783U JP H0145273 Y2 JPH0145273 Y2 JP H0145273Y2
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JP
Japan
Prior art keywords
inverter
output
signal
frequency
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1382783U
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Japanese (ja)
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JPS59122791U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Priority to JP1382783U priority Critical patent/JPS59122791U/en
Publication of JPS59122791U publication Critical patent/JPS59122791U/en
Application granted granted Critical
Publication of JPH0145273Y2 publication Critical patent/JPH0145273Y2/ja
Granted legal-status Critical Current

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Description

【考案の詳細な説明】 本考案は負荷にLC共振回路を有する電流形イ
ンバータの制御装置に関する。
[Detailed Description of the Invention] The present invention relates to a control device for a current source inverter having an LC resonant circuit in the load.

誘導加熱用電流形インバータなど、負荷にLC
共振回路(タンク回路)を有する電流形インバー
タは、例えば第1図に示す主回路構成にされる。
順変換器1によつて変換された直流電力は直流リ
アクトル2を通して定電流化され、サイリスタブ
リツジ構成のインバータ本体3によつて負荷4の
LC共振回路の共振周波数に一致する交流電流に
変換されて該負荷4に供給される。
LC for loads such as current source inverters for induction heating
A current source inverter having a resonant circuit (tank circuit) has a main circuit configuration shown in FIG. 1, for example.
The DC power converted by the forward converter 1 is made into a constant current through the DC reactor 2, and is converted into a constant current by the inverter body 3 having a thyristor bridge configuration.
It is converted into an alternating current that matches the resonant frequency of the LC resonant circuit and is supplied to the load 4.

インバータ本体3のサイリスタTH1〜TH4
の転流は負荷の誘起電圧によつて逆バイアスをか
けて転流するため、サイリスタTH1〜TH4に
は進み位相角で点弧させる。第2図は転流時の電
圧Vout、電流Iout及びゲート信号タイミングを
示す。同図において、サイリスタの点弧角βはゲ
ート信号印加時点t1からそれまでオン状態のサイ
リスタに逆電圧が印加開始されるまでの重なり時
間μと、逆電圧印加期間になる転流余裕時間τに
分けられ、サイリスタには転流余裕時間τが確保
できるようサイリスタのゲート制御をする。
Thyristors TH1 to TH4 of inverter main body 3
Since the commutation is performed by applying a reverse bias by the induced voltage of the load, the thyristors TH1 to TH4 are fired at an advanced phase angle. FIG. 2 shows the voltage Vout, current Iout, and gate signal timing during commutation. In the figure, the firing angle β of the thyristor is determined by the overlap time μ from the gate signal application time t 1 until the application of the reverse voltage to the thyristor that has been in the on state until then starts, and the commutation margin time τ during the reverse voltage application period. The gate of the thyristor is controlled to ensure commutation margin time τ for the thyristor.

従来の制御装置は、第3図に示す構成にされて
転流余裕時間τが確保される。同図における各部
波形は第4図になる。インバータ出力電圧Vout
(第4図の信号a)はフイルタ回路11を通して
基本波成分のみが取出され、この信号(第4図の
b)から零クロス検出器12によつてその零点タ
イミング信号(第4図のc)が検出されてフリツ
プフロツプ13のリセツト信号にされる。一方、
インバータ出力電流Iout(第4図のf)は零クロ
ス検出器14によつてその零点タイミング信号
(第4図のg)が検出されてフリツプフロツプ1
5のリセツト信号にされる。フリツプフロツプ1
3及び15はそのセツト信号に後述の電圧−周波
数変換器20の出力が与えられ、この出力(第4
図のl)はインバータ本体の点弧角βになつてフ
リツプフロツプ13のセツト期間(第4図のd)
は点弧角βに相当し、フリツプフロツプ15のセ
ツト期間(第4図のh)は重なり時間μの半分
(μ/2)に相当する。
The conventional control device has the configuration shown in FIG. 3 to ensure commutation margin time τ. The waveforms of each part in the figure are shown in FIG. 4. Inverter output voltage Vout
Only the fundamental wave component (signal a in FIG. 4) is extracted through the filter circuit 11, and the zero point timing signal (c in FIG. 4) is extracted from this signal (b in FIG. 4) by the zero cross detector 12. is detected and used as a reset signal for the flip-flop 13. on the other hand,
The inverter output current Iout (f in FIG. 4) is detected by the zero cross detector 14 at its zero point timing signal (g in FIG. 4), and the inverter output current Iout (f in FIG.
5 reset signal. flipflop 1
3 and 15, the output of a voltage-frequency converter 20 (described later) is given to the set signal, and this output (fourth
l) in the figure is the setting period of the flip-flop 13 (d in Figure 4) when the firing angle β of the inverter body is reached.
corresponds to the firing angle β, and the setting period of the flip-flop 15 (h in FIG. 4) corresponds to half (μ/2) of the overlap time μ.

フリツプフロツプ13の出力は利得1の積分回
路16で積分されて平均化直流電圧信号(第4図
のe)に変換され、フリツプフロツプ17の出力
は利得−2の積分回路17で積分されて平均化直
流電圧信号(第4図のi)に変換されて重なり角
μに相当する電圧信号が取出される。これら信号
はτ設定器18に設定(サイリスタTH1〜TH
4によつて決まる)される転流余裕角τに相当す
る直流電圧(第4図のj)が加算されて比較さ
れ、この3つの信号の偏差が偏差増幅器19で増
幅され(第4図のk)、電圧−周波数変換器20
の電圧入力にされる。この変換器20の出力はフ
リツプフロツプ13,15のセツト信号になるほ
かに、ゲート回路21のゲート位相信号にされ、
ゲート回路21のゲート出力によつてサイリスタ
TH1〜TH4の点弧制御がなされる。すなわち、
点弧角βと重なり角μ、転流余裕角τの差が零に
なるように電圧−周波数変換器20の出力パルス
位相が制御され、転流余裕角τの確保がなされ
る。
The output of the flip-flop 13 is integrated by an integrator circuit 16 with a gain of 1 and converted into an averaged DC voltage signal (e in FIG. 4), and the output of the flip-flop 17 is integrated by an integrator circuit 17 with a gain of -2 and converted into an averaged DC voltage signal (e in FIG. 4). It is converted into a voltage signal (i in FIG. 4) and a voltage signal corresponding to the overlap angle μ is extracted. These signals are set in the τ setting device 18 (thyristors TH1 to TH
The DC voltage (j in Fig. 4) corresponding to the commutation margin angle τ (determined by 4) is added and compared, and the deviation of these three signals is amplified by the deviation amplifier 19 ( k), voltage-frequency converter 20
voltage input. The output of this converter 20 is used not only as a set signal for flip-flops 13 and 15, but also as a gate phase signal for a gate circuit 21.
The thyristor is controlled by the gate output of the gate circuit 21.
Ignition control of TH1 to TH4 is performed. That is,
The output pulse phase of the voltage-frequency converter 20 is controlled so that the difference between the firing angle β, the overlap angle μ, and the commutation margin angle τ becomes zero, thereby ensuring the commutation margin angle τ.

ここで、偏差増幅器19にはその出力を制限す
るτリミツタ回路22が設けられる。τリミツタ
回路22は、電圧Vout、電流Ioutの信号がフイ
ードバツクされない始動時のゲート信号位相をτ
に制限するもので、そのリミツタ値は電圧−周波
数変換器20のリミツタ出力周波数の1/2(単相)
の周波数と負荷4のタンク回路周波数とのマツチ
ングがとれるように決定される。このマツチング
については、タンク回路周波数に対して変換器2
0のリミツタ出力の1/2周波数が−40%程度まで
ずれても安定に始動できるがこれ以上の周波数ず
れは始動不安定になる。一方、タンク回路周波数
の半周期Tが変換器22のリミツタ出力周期T0
よりも短かくなると、τ一定制御が不能となり、
サイリスタの転流余裕時間は設定値よりもT0
Tの時間だけ短かくなる。
Here, the deviation amplifier 19 is provided with a τ limiter circuit 22 that limits its output. The τ limiter circuit 22 sets the gate signal phase at τ when the voltage Vout and current Iout signals are not fed back.
The limiter value is 1/2 (single phase) of the limiter output frequency of the voltage-frequency converter 20.
The frequency is determined so that the frequency of the load 4 matches the tank circuit frequency of the load 4. For this matching, converter 2
Even if the 1/2 frequency of the 0 limiter output deviates by about -40%, stable starting is possible, but if the frequency deviates beyond this, starting becomes unstable. On the other hand, the half period T of the tank circuit frequency is the limiter output period T 0 of the converter 22.
If it becomes shorter than , constant τ control becomes impossible,
The commutation margin time of the thyristor is T 0 − than the set value.
It becomes shorter by the time T.

従つて、負荷4のタンク回路周波数に応じてイ
ンバータ装置の定格出力周波数を変え、そのτリ
ミツタ回路22のリミツタ値も変える必要がある
し、インバータ装置の出力周波数範囲も限定され
て装置の利用効率が悪くなる。
Therefore, it is necessary to change the rated output frequency of the inverter device according to the tank circuit frequency of the load 4, and also change the limiter value of the τ limiter circuit 22, and the output frequency range of the inverter device is also limited, which reduces the utilization efficiency of the device. becomes worse.

本考案は上述までの事情に鑑みてなされたもの
で、τリミツタ回路のリミツタ値を負荷タンク回
路周波数に応じて切換える手段を設けることによ
り、広い出力周波数範囲に渡つてτ一定制御を確
実、容易にして装置の汎用性を高めかつ取扱いを
容易にしたインバータの制御装置を提供すること
を目的とする。
The present invention was developed in view of the above-mentioned circumstances, and by providing a means for switching the limiter value of the τ limiter circuit according to the load tank circuit frequency, constant τ control can be reliably and easily performed over a wide output frequency range. An object of the present invention is to provide an inverter control device that increases the versatility of the device and facilitates handling.

第5図は本考案の一実施例を示し、出力周波数
を2段切換えする場合である。同図が第3図と異
なる部分は、偏差増幅器19に設けるτリミツタ
回路に互いに異なるリミツタ値を持つ2つの回路
22A,22Bを用意し、このτリミツタ回路2
2A,22Bの一方を切換スイツチ23で切換え
て偏差増幅器19の出力制限回路として作用させ
る点にある。切換スイツチ23はオン・オフ切換
信号FCによつて切換えられる。
FIG. 5 shows an embodiment of the present invention, in which the output frequency is switched in two stages. The difference between this figure and FIG. 3 is that two circuits 22A and 22B having mutually different limiter values are prepared in the τ limiter circuit provided in the deviation amplifier 19, and the τ limiter circuit 2
The point is that one of 2A and 22B is switched by a changeover switch 23 to function as an output limiting circuit for the deviation amplifier 19. The changeover switch 23 is switched by an on/off changeover signal FC.

こうした構成において、信号FCを制御するこ
とによつてτリミツタ回路22A,22Bの何れ
か一方が偏差増幅器19のリミツタ値を制御し、
インバータ装置の出力周波数切換えに応じてτ一
定制御を可能にする。
In such a configuration, either one of the τ limiter circuits 22A and 22B controls the limiter value of the deviation amplifier 19 by controlling the signal FC,
Enables constant τ control according to output frequency switching of the inverter device.

従つて、本考案によれば、負荷の変更による
LC共振回路周波数の違いはτリミツタ回路を該
周波数に適合したものに切換えることで済み、イ
ンバータ本体3のサイリスタに必要とする転流余
裕角を確保するのに切換信号FCの制御、操作の
みで種々の負荷に適用できるインバータ装置にな
る。
Therefore, according to the present invention, by changing the load,
Differences in LC resonant circuit frequency can be detected by switching the τ limiter circuit to one suitable for the frequency, and only controlling and operating the switching signal FC can secure the commutation margin angle required for the thyristor in the inverter main body 3. The inverter device can be applied to various loads.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は電流形インバータの主回路構成図、第
2図は第1図における転流余裕時間の説明のため
の波形図、第3図は従来の制御装置回路図、第4
図は第3図の各部波形図、第5図は本考案の一実
施例を示す制御装置回路図である。 3……インバータ本体、4……負荷、11……
フイルタ回路、12,14……零クロス検出器、
13,15……フリツプフロツプ、16,17…
…積分回路、18……τ設定回路、19……偏差
増幅器、20……電圧−周波数変換器、21……
ゲート回路、22,22A,22B……τリミツ
タ回路、23……切換スイツチ。
Fig. 1 is a main circuit configuration diagram of a current source inverter, Fig. 2 is a waveform diagram for explaining the commutation margin time in Fig. 1, Fig. 3 is a conventional control device circuit diagram, and Fig. 4 is a diagram of a conventional control device.
The figure is a waveform diagram of each part of FIG. 3, and FIG. 5 is a circuit diagram of a control device showing an embodiment of the present invention. 3... Inverter main body, 4... Load, 11...
Filter circuit, 12, 14... zero cross detector,
13,15...flipflop, 16,17...
...Integrator circuit, 18...τ setting circuit, 19... Deviation amplifier, 20... Voltage-frequency converter, 21...
Gate circuit, 22, 22A, 22B...τ limiter circuit, 23... Changeover switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 負荷にLC共振回路を有する電流形サイリスタ
インバータにおいて、インバータ出力電圧及び出
力電流波形の零クロスタイミング信号とインバー
タ出力周波数制御信号のタイミング信号との時間
差からインバータ主回路サイリスタの点弧角
(β)、重なり時間(μ)に対応する直流信号を検
出し、この検出信号と上記サイリスタの転流余裕
時間(τ)に対応する直流信号の偏差を得る偏差
増幅器の出力を上記インバータ出力周波数制御信
号の周波数制御信号とし、上記偏差増幅器の出力
リミツタ値を負荷のLC共振回路の共振周波数に
応じて上記転流余裕時間(τ)を一定に制御する
値に切換える切換手段を設けたことを特徴とする
電流形インバータの制御装置。
In a current source thyristor inverter with an LC resonant circuit in the load, the firing angle (β) of the inverter main circuit thyristor is determined from the time difference between the zero cross timing signal of the inverter output voltage and output current waveforms and the timing signal of the inverter output frequency control signal. Detect the DC signal corresponding to the overlap time (μ), and obtain the deviation between this detection signal and the DC signal corresponding to the commutation margin time (τ) of the thyristor.The output of the deviation amplifier is set to the frequency of the inverter output frequency control signal. A current characterized in that the control signal is provided with a switching means for switching the output limiter value of the deviation amplifier to a value that controls the commutation margin time (τ) to a constant value according to the resonant frequency of the LC resonant circuit of the load. Control device for type inverter.
JP1382783U 1983-02-02 1983-02-02 Current source inverter control device Granted JPS59122791U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1382783U JPS59122791U (en) 1983-02-02 1983-02-02 Current source inverter control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1382783U JPS59122791U (en) 1983-02-02 1983-02-02 Current source inverter control device

Publications (2)

Publication Number Publication Date
JPS59122791U JPS59122791U (en) 1984-08-18
JPH0145273Y2 true JPH0145273Y2 (en) 1989-12-27

Family

ID=30145204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1382783U Granted JPS59122791U (en) 1983-02-02 1983-02-02 Current source inverter control device

Country Status (1)

Country Link
JP (1) JPS59122791U (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5429955B2 (en) * 2008-08-01 2014-02-26 北芝電機株式会社 Current source inverter

Also Published As

Publication number Publication date
JPS59122791U (en) 1984-08-18

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