JPS631836B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inverter control circuit that includes a plurality of thyristors and converts DC voltage into AC voltage.

The inverter to which this invention is applied is as shown in FIG. In FIG. 1, a DC power supply 1 supplies a pulse current I ₀ corresponding to one phase of a three-phase AC current to a load 3 through an inverter 2. Inverter 2 is controlled by a control circuit (not shown). That is, the inverter 2 includes thyristors 4 and 5 that are connected in series between the output ends of the DC power source 1 and thyristors 6 and 7 that are similarly connected in series and connected in parallel to the thyristors 4 and 5. Furthermore, a reactor 8 and a capacitor 9 are connected in series between the connection point of the thyristors 4 and 5 and the connection point of the thyristors 6 and 7.

FIG. 2 is a waveform diagram illustrating the operation of the inverter 2. In Figure 2, a, b, c and d are
Gate signals 6a, 4a, 7a, and 5a are shown applied to the gates of thyristors 6, 4, 7, and 5, respectively. Until time t ₀ , thyristor 6 is on, thyristor 4 is on, and current I ₀ flows through thyristor 6 to load 3 . At time _t0 , the gate signal 6a is turned off and the gate signal 4a is turned on, so the thyristor 4 is turned on. As a result, a resonant current flows through the capacitor 9 and the reactor 8, which have been charged with the illustrated polarity, so that the thyristor 6 is first extinguished. At time t ₁ ,
The gate current 7a is turned on, turning on the thyristor 7, and the thyristor 4 is also turned off at time _t2 , thus completing the commutation.

Since the load 3 is also supplied with alternating current from an inverter of another phase (not shown), the current from the load 3 flows through the thyristor 7. At time _t3 , the gate signal 7a is turned off and the gate signal 5a is turned on, so the thyristor 5 is turned on, and the thyristor 7 is turned off by the same operation as described above, and then the thyristor 5 is turned off.

If the periods of the gate signals 4a, 6a, 7a, and 5a are shortened in order to increase the frequency of such commutation, a state will be reached in which the thyristor 5 is fired before the thyristor 4 is extinguished. Since this condition short-circuits the output end of power supply 1,
The frequency must be limited to that before reaching this state. That is, commutation between the thyristors 6 and 7 requires a commutation prohibition time, that is, a pulse-off period, to prevent a short circuit in the power supply.

Conventionally, there has been no inverter control circuit that can detect such a pulse off period and indicate that the inverter can operate properly.

This invention was made to solve the above-mentioned problems, and when obtaining a gate signal, it is possible to properly operate the inverter by obtaining a signal indicating whether or not the pulse-off period of the inverter is satisfied. The purpose of this invention is to obtain a control circuit for an inverter that can be operated.

Details will be described below with reference to the circuit diagram of FIG. 3 showing an embodiment of the present invention and the waveform chart of FIG. 4 showing waveforms of its operation. In FIG. 3, the carrier wave signal generating circuit 10 generates the carrier wave signal shown in FIG. 10a, the modulated wave signal generation circuit 1
1 generates a modulated wave signal 11a shown in FIG. 4a. The comparison circuit 12 which receives the carrier wave signal 10a and the modulated wave signal 11a outputs a signal 12a (FIG. 4b) which becomes low during a period in which the former is greater than the latter. Signal generation circuit 1 that inputs this signal 12a
3 detects the rising edge of the input signal 12a and generates a signal 13a with a pulse width corresponding to the minimum pulse off period.
(Figure 4c) is output. This signal 13a is input to an OR gate 14 and a detection circuit 16. The inverter 15 receives the output signal 12 of the comparator circuit 12.
a is inverted and inputted to the detection circuit 16 as a signal 15a (FIG. 4d).

This detection circuit 16 receives the above-mentioned signals 13a and 15a.
is input, the pulse width of the output signal 12a of the comparison circuit 12 is checked using the signal 13a, and if the above-mentioned period is not satisfied, the signal 16a shown in FIG.

The OR gate 14 has signals 12a, 13a
A logical sum is taken between them, and a signal 14a shown in FIG.

Similar to the signal generating circuit 13, the signal generating circuit 17 generates a signal 1 with a pulse width corresponding to the minimum pulse off period determined from the commutation turn off time of the thyristor, etc.
7a is generated by detecting the fall of the signal 14a.
The signal 17a (FIG. 4g) is then input to the OR gate 19 and the detection circuit 20. OR gate 19 takes the logical sum of signals 17a and 18a and its inversion, and outputs signal 19a shown in FIG. 4j. This signal 19a serves as a gate signal for the thyristors 4 to 7 constituting the inverter shown in FIG.
The inverter 18 and the OR gate 19 constitute a gate signal output circuit.

On the other hand, the detection circuit 20 receives the signal 17a and the signal 14a similarly to the detection circuit 16, and receives the signal 17a and the signal 14a.
The pulse width of the output signal 14a of the OR gate 14 is checked by a, and if the minimum off-pulse period is not satisfied, the signal 2 in FIG. 4h indicating prohibition of commutation is detected.
0a and supplies it to the OR gate 21. In this description, the prohibition of commutation is indicated by the signal 16a, and the signal 20a indicates the case where the minimum off-pulse period that does not require prohibition of commutation is satisfied. The OR gate 21 receives the signals 16a,
20a is taken, and a signal 21a indicating prohibition of commutation of the thyristor shown in FIG. 4k is output. This signal 21a is a signal indicating prohibition of commutation of the thyristor constituting the inverter, that is, a signal indicating a pulse off period. Therefore, this signal 21a
By limiting the frequency of commutation using
The inverter can be operated properly.

Note that the above embodiment describes one phase of a polyphase alternating current, and control circuits having the same configuration as the above embodiment are provided for other phases as well. Also, based on its logical function, such a control circuit
Obviously, various modifications can be easily achieved.

As described above, according to the present invention, when obtaining the gate signal of the thyristor constituting the inverter, a signal indicating whether the pulse off period of the inverter is satisfied, that is, a signal prohibiting commutation of the thyristor is output. This has the effect of making it easier to properly operate the inverter.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an inverter, FIG. 2 is a waveform diagram of a gate signal that operates the inverter shown in FIG. 1, FIG. 3 is a circuit diagram of an inverter control circuit showing an embodiment of the present invention, and FIG. The figure is a waveform diagram of the operation of the control circuit shown in FIG. 3. 10, 11, 13, 17...signal generation circuit, 1
2...Comparison circuit, 16, 20...Detection circuit.

Claims (1)

[Claims] 1 an inverter made up of a plurality of thyristors, a carrier wave signal generation circuit that generates a carrier wave signal in relation to an alternating current voltage output from the inverter, and a modulated wave signal generation circuit that generates a modulated wave signal; A comparison circuit detects a period exceeding the modulated wave signal level, and a pulse signal having a pulse width corresponding to a period in which commutation of a thyristor constituting the inverter is to be prohibited by detecting a change point in the output of this comparison circuit. a gate signal output circuit that outputs a gate signal of a thyristor forming the inverter based on the pulse signal or the output of the comparison circuit; and a gate signal output circuit that outputs a gate signal of the thyristor forming the inverter based on the pulse signal or the output of the comparison circuit; and a detection circuit that outputs a signal indicating prohibition of commutation when the period is not satisfied.