JP2867451B2 - Frequency tuning circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency tuning circuit used in a power converter for supplying alternating-current power to a resonance circuit.

[Conventional technology]

When the load of the power conversion device is an inductance load such as an induction heating device or an induction melting furnace, it is common to insert a resonance capacitor 4 and operate at a frequency (tuning frequency) fo very close to the resonance frequency. The frequency tuning is performed so that the output frequency f of the inverter 2 becomes the tuning frequency fo. For tuning, it is necessary to control the phase difference between the inverter output voltage and the output current to be zero or to delay the phase of the voltage of the resonance capacitor by 90 ° from the output voltage. Since both can be controlled by basically the same means, a case where the voltage of the resonance capacitor is detected will be described below.

FIG. 3 shows a conventional frequency tuning circuit of this kind. In the figure, reference numeral 1 denotes a single-phase commercial power supply, and 2 denotes a single-phase inverter, which converts a commercial alternating current into a direct current by a rectifier 2A, and then converts the commercial alternating current into an alternating current of a required frequency by an inverter 2B. 3
Is a reactor, 4 is a condenser, and 5 is a heating coil of an induction heating device (5A is for inductance, and 5B is for resistance). The inverter section 2B of the inverter 2 has a bridge connection of four transistors Tr.
Has a flywheel diode D connected in anti-parallel.
6 turns on / off the transistor Tr that constitutes the inverter section 2B
A driving circuit 7 for driving is a voltage / frequency converter (V / F converter), and sends a frequency command F ^* to the driving circuit 6. Reference numeral 8 denotes a voltage detector for detecting the output voltage Vo of the inverter 2, and the detected voltage is shaped by a comparator 8A. Reference numeral 9 denotes a voltage detector for detecting the voltage Vc across the capacitor 4. The detected voltage is shaped into a rectangular wave by a comparator 9A. Reference numeral 10 denotes an exclusive OR circuit (hereinafter, referred to as exclusive OR), to which the output voltage Vo 'of the comparator 8A and the output voltage Vc' of the comparator 9A are input. 11 is an integrator, exclusive
Output V.phi of OR10 (for convenience of explanation, the pulse height is also a V.phi) and with a differential voltage between the bias voltage V _B by integrating the V.phi ',
The integrated value V _IN is sent to the V / F converter 7. 12 is a bias circuit, and sends the bias voltage V _B. The bias voltage V _B is set to be V _B = V.phi / 2.

In the configuration of FIG. 3, when the inverter output frequency f is the tuning frequency fo (FIG. 4 (a)), the voltage Vo 'and the voltage Vc' have a phase difference of 90 [deg.]. Is a signal having a waveform in which the period of the positive period is equal to the period of the level L. If the output (one cycle average value) of the integrator 11 at this time is V _IN ', the V / F converter 7 outputs a frequency command whose value is the tuning frequency fo while the input is V _IN '. F ^* is sent to the drive circuit 6. When the tuning is deviated, for example, as shown in FIG. 4 (b) (example when the tuning frequency is high) and FIG. 4 (c) (example when the tuning frequency is low),
Since the level H period and the level L period of the output Vφ of the exclusive OR 10 are not equal, the output of the integrator 11 fluctuates with respect to V _IN ′, and the frequency command F ^* changes in accordance with the fluctuation. However, the inverter frequency f is raised or lowered toward the tuning frequency.

[Problems to be solved by the invention]

In this manner, the frequency tuning is performed. In a usage method in which the inverter 2 is started and its output frequency f is raised from the low frequency region to the tuning frequency to perform frequency tuning, the inverter output frequency f is adjusted to the tuning frequency. fo 1 /
As shown in FIG. 5, the voltage Vφ ′ changes from H to L and from L to H during the period in which the voltage Vo ′ is H or L, as shown in FIG. Becomes zero, the output of the integrator 11 becomes the same as that at the time of tuning, and the inverter output frequency f is locked at fo / 3, and does not rise to the tuning frequency.

For this reason, conventionally, the output difference between the frequency of Vo ′ and the frequency of Vc ′ is monitored through a frequency / voltage converter, and when the difference is equal to or more than a predetermined value, the output difference is integrated. The lock state is forcibly released by adding to the input of the power converter. However, when the power converter is driven at a high frequency, it is difficult to obtain good accuracy and the frequency / conversion is difficult. There was a problem that a vessel required a considerably expensive thing.

The present invention has been made to solve the above problems,
An object of the present invention is to provide a frequency tuning circuit that can avoid 1/3 tuning without using expensive circuit components.

[Means for solving the problem]

In order to achieve the above object, the present invention relates to a case where the voltage of a capacitor changes in two directions from positive to negative and from negative to positive during a positive or negative half-wave period of an output voltage of a power converter. And a signal of a predetermined level when the change in the two directions is stored by checking the contents of the storage circuit at the end of each of the positive or negative half-wave periods. Is provided with a determination circuit for adding the value to

[Action]

According to the present invention, when a 1/3 tuning state is established, the storage circuit stores the state, and the determination circuit for checking the contents of the storage circuit adds a signal of a predetermined level to the input signal to the integrator. Changes, and 1/3 entrainment is forcibly released.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, reference numeral 21 denotes a control power supply of a voltage Vk. 22 and
Reference numeral 23 denotes a storage circuit (D-flip-flop, hereinafter referred to as FF), and a voltage Vk is applied to a data input (D input) of FF22.
Are coupled, a voltage Vc 'is supplied to a clock input (CL input), and a voltage Vo' is input to a reset input (input). The voltage Vk is coupled to the data input (D input) of the FF23, a signal obtained by inverting the polarity of the voltage Vc 'by the inverter 24 is supplied to the clock input (CL input), and the voltage Vo is applied to the reset input (input). 'Is input. Outputs Q ₁ and Q ₂ of both FFs 22 and 23 are supplied to one and the other terminals of a NAND gate 25, and an output A _{1 of the} NAND gate 25 is supplied to an S input of a storage circuit (RS flip-flop) 26. A voltage Vo ′ through a delay element (delay time ΔT) 27 is input to the reset input of the FF 26. The output Q ₃ of the FF26 is applied to the D input of the decision circuit (D-flip-flop) 28, the clock input CL of FF28 is the signal obtained by inverting the voltage Vo 'by the inverter 29 is input. The output Q ₄ of the FF 28 is input to the integrator 11 through the inverter 30.

FIG. 2 (a) shows the output waveform of each part at the time of 1/3 tuning.

In this configuration, FF22 is the voltage during the positive period of the voltage Vo '.
It stores whether or not Vc 'has risen. That is, the output Q ₁ is' when is positive, Vc 'voltage Vo rises in synchronism with the rising of, it falls in synchronization with the falling of the Vo'. The FF23 stores whether the voltage Vc 'has fallen during the positive period of the voltage Vo'. That is, the output Q ₂ is' when is positive, Vc 'voltage Vo rises in synchronization with the falling of, Vo'
Falls in synchronism with the fall of. And the NAND gate
Since the output A ₁ of the 25 falls when the output Q _1, Q ₂ becomes H level, the fall is output Q ₃ of synchronization with FF26 rises, the output Q ₃ are at delay element 27 the voltage Vo ' It falls in synchronization with the falling of the signal a ₂ which is delayed. That is, the FF 26 stores the voltage Vc 'when both "falling" and "rising" occur in the positive period of the voltage Vo' (1/3 tuning state). When in this 1/3 tuning state, the output Q _{3 of} FF26
Before but that falls, since rises CL input of FF28, the output Q ₄ of FF28 becomes the H level, the input V of this value integrator 11
φ ′, the output of the integrator 11 is
V _IN ′, the frequency command F ^* changes in a direction to increase the inverter output frequency f, and increases toward the tuning frequency.

Figure 2 (b) is shows the waveforms of various portions when the inverter frequency reaches the tuning frequency fo, at the time of this tuning, the output Q ₃ of the memory circuit 26 is at the L level, the determination circuit
Output Q ₄ of 28 even in L level, the integrator 11 signals V.phi '
Only calculate.

As described above, in the present embodiment, since the 1/3 tuning state is logically determined to escape from the 1/3 tuning state, it can be configured using a general-purpose logic element. Is operated in a high frequency range, it can be cheaper and more reliable than the conventional case using a frequency / voltage converter.

〔The invention's effect〕

As described above, the present invention logically determines whether or not 1/3 tuning has been performed, and when 1/3 tuning has been performed, a signal of a predetermined level is added to the input of the integrator, and the By using a configuration in which the output is forcibly changed, it is possible to obtain a circuit for canceling 1/3 tuning by combining logic elements. Can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
3 (b) and 3 (b) are waveform time charts showing waveforms of respective parts of the embodiment, FIG. 3 is a circuit diagram showing a conventional frequency tuning circuit, and FIGS. 4 (a) to 4 (c) explain the operation of the frequency tuning circuit. FIG. 5 is a waveform chart for explaining the problems of the conventional example. 2 ... Inverter as power converter, 2A ... Rectifier, 2B
... Inverter part, 4 ... Resonant capacitor, 5 ... Load, 6 ... Drive circuit, 7 ... V / F converter, 10 ... Exclusive O
R, 11 ... integrator, 22, 23, 26 ... flip-flop as a storage circuit, 27 ...
... delay element, 28 ... flip-flop as a judgment circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H02M 7/42-7/98 H05B ⁶ /02-6/06 H05B 6/12

Claims (1)

(57) [Claims] 1. A logic circuit for transmitting a pulse having a pulse width corresponding to a phase shift between an output voltage of a power converter for supplying AC power to a resonance circuit and a voltage or an output current of a capacitor of the resonance circuit. An integrator that integrates the output of the circuit,
In a frequency tuning circuit having a voltage / frequency converter to which the output of the integrator is input and providing the output of the voltage / frequency converter to the power converter as a frequency command, the output voltage of the power converter is corrected. Alternatively, when the voltage or output current of the capacitor exhibits a change in two directions from positive to negative and from negative to positive during the negative half-wave period, a storage circuit for storing the change, A determination circuit is provided for reading out the contents of the storage circuit at each end and adding a signal of a predetermined level to the input signal of the integrator in a frequency increasing direction when the change in the two directions is stored. Frequency tuning circuit.