JPH0446073B2 - - Google Patents
Info
- Publication number
- JPH0446073B2 JPH0446073B2 JP59010597A JP1059784A JPH0446073B2 JP H0446073 B2 JPH0446073 B2 JP H0446073B2 JP 59010597 A JP59010597 A JP 59010597A JP 1059784 A JP1059784 A JP 1059784A JP H0446073 B2 JPH0446073 B2 JP H0446073B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- current
- sine wave
- command
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010586 diagram Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007493 shaping process Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
- H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Description
【発明の詳細な説明】
この発明は正弦波PWM制御のトランジスタイ
ンバータに関する。交流電動機の可変速駆動を行
う場合、電動機電流を正弦波とする正弦波PWM
制御のトランジスタインバータがよく用いられ
る。第1図にトランジスタインバータ1相分のブ
ロツク図を示すが、正弦波の電流指令と検出の電
動機電流を比較、偏差を得、これを正弦波制御電
圧指令としてキヤリヤ三角波と比較し、先の電流
指令に対応した電動機電流を供給するよう、トラ
ンジスタをオン/オフ制御しインバータ出力電圧
の平均値を正弦波とするものである。すなわち、
電流調節器1を介し増幅された正弦波電圧は比較
器2にてキヤリヤ三角波と比較され、電流指令に
対応した幅のパルス波形を生成し、一方のトラン
ジスタ3のベース入力として、かつその反転信号
が他方トランジスタ4のベース入力としてそれぞ
れ使用される。なお、この上下トランジスタ3,
4のベース入力は、これらトランジスタ3,4の
双方がともに導通し電源短絡となるのを防ぐべ
く、オフからオンの立上りのタイミングをずらし
若干のタイムラグを設けており(波形整形回路
5,6による)、トランジスタの一方が導通状態
になるタイミングは、他方のトランジスタが必ら
ず不導通の状態に切替つてから後になるよう設定
されている。第1図において、7はキヤリヤ三角
波を供給する発振器、8は反転パルス波形を形成
の符号変換器、9,10はベースドライブ回路、
11,12はトランジスタ3,4に逆並列接続の
ダイオード、13は電流検出器、14は電動機負
荷の一相分、15,16は直流電源である。第2
図のタイムチヤートは、キヤリヤ三角波aと、電
流調節器1出力の正弦波制御電圧波形b、比較器
2出力の、第1のトランジスタ3ベース入力信号
のパルス波形C1とその反転波形の、第2のトラ
ンジスタ4ベース入力信号波形C2、をそれぞれ
表わす。第3図のタイムチヤートは、波形整形回
路5,6の入・出力パルス波形の関係を示すもの
で、出力側のパルス波形立上りは入力のパルス波
形より若干のタイムラグを有し、この結果、双方
のトランジスタ3,4の導通・不導通の切替わり
時に必らずデツドタイムを生じ、双方ともオフに
なる期間を備える。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sine wave PWM controlled transistor inverter. When performing variable speed drive of an AC motor, use sine wave PWM that makes the motor current a sine wave.
Controlled transistor inverters are often used. Figure 1 shows a block diagram for one phase of a transistor inverter. Compare the sine wave current command and the detected motor current, obtain the deviation, use this as a sine wave control voltage command, and compare it with the carrier triangular wave. The transistor is controlled on/off to supply a motor current corresponding to the command, and the average value of the inverter output voltage is made into a sine wave. That is,
The sine wave voltage amplified through the current regulator 1 is compared with the carrier triangular wave in the comparator 2 to generate a pulse waveform with a width corresponding to the current command, and is used as the base input of one transistor 3 and its inverted signal. are respectively used as base inputs of the other transistor 4. Note that the upper and lower transistors 3,
In order to prevent both transistors 3 and 4 from conducting and shorting the power supply, the base input of transistor 4 has a slight time lag by shifting the timing of the rise from off to on (by waveform shaping circuits 5 and 6). ), the timing at which one of the transistors becomes conductive is set so that the timing at which one of the transistors becomes conductive is always after the other transistor is switched to a non-conductive state. In FIG. 1, 7 is an oscillator that supplies a carrier triangular wave; 8 is a code converter that forms an inverted pulse waveform; 9 and 10 are base drive circuits;
11 and 12 are diodes connected in antiparallel to the transistors 3 and 4, 13 is a current detector, 14 is one phase of the motor load, and 15 and 16 are DC power supplies. Second
The time chart in the figure shows the carrier triangular wave a, the sine wave control voltage waveform b of the current regulator 1 output, the pulse waveform C 1 of the first transistor 3 base input signal of the comparator 2 output, and its inverted waveform. 2 and 4 represent the transistor 4 base input signal waveform C 2 , respectively. The time chart in Figure 3 shows the relationship between the input and output pulse waveforms of the waveform shaping circuits 5 and 6. The rise of the pulse waveform on the output side has a slight time lag than the input pulse waveform, and as a result, A dead time always occurs when the transistors 3 and 4 are switched between conduction and non-conduction, and there is a period in which both transistors are turned off.
このように、正弦波PWM制御のトランジスタ
インバータでは、電源短絡の危険を防ぐため、こ
れらトランジスタの切替わり時双方共オフになる
デツドタイム区間を設けることが不可欠で、この
ことは、電動機電流の減少しインバータ出力電圧
平均値の低下する程、その占める割合が増大し、
制御不能領域の拡大となつて現われる。すなわ
ち、この種インバータは無負荷とか軽負荷の微少
電流領域において制御性能の低下を来たし、応答
遅れ等の問題を発生する。 Thus, in sinusoidal PWM controlled transistor inverters, it is essential to provide a dead time period in which both transistors are turned off when switching, in order to prevent the risk of power supply short circuits. As the average value of the inverter output voltage decreases, its proportion increases.
It appears as an expansion of uncontrollable areas. That is, this type of inverter suffers from a decrease in control performance in the micro current region of no load or light load, and causes problems such as response delay.
ところで、第2図において電圧指令bに対応し
て電動機電流が図示するd波形のような位相で流
れたとすれば、負の領域では、図示する斜線区間
でトランジスタ3にオン指令が与えられているに
拘わらずダイオード11に電流が流れており、ま
た正の領域でも同じく破線区間でトランジスタ4
にオン指令が与えられるが実際の電動機電流はダ
イオード12を介して流れることになる。すなわ
ち、電動機電流の連続して流れている状態では、
逆並列接続のダイオード11,12が導通してい
る期間においても、主回路トランジスタ3,4に
オン指令が与えられ、無駄なベース電力を消費
し、またオン指令を供給するベース入力回路にあ
つても不必要な電力損失を来たす。 By the way, in FIG. 2, if the motor current flows in a phase like the waveform d shown in the diagram in response to the voltage command b, then in the negative region, an ON command is given to the transistor 3 in the hatched area shown in the diagram. Regardless of the current, current flows through the diode 11, and even in the positive region, the current flows through the transistor 4 in the dashed line section.
An on command is given to the motor, but the actual motor current flows through the diode 12. In other words, when the motor current is flowing continuously,
Even during the period when the anti-parallel connected diodes 11 and 12 are conducting, an ON command is given to the main circuit transistors 3 and 4, which consumes wasteful base power, and the base input circuit supplies the ON command. also causes unnecessary power loss.
この発明は、上記に鑑み電流の連続して流れて
いる状態において、逆並列接続ダイオードの導通
の際に主回路トランジスタのオン/オフ指令を遮
断し、主回路トランジスタ及びそのベース駆動回
路の電力損失を軽減するとともに、上記キヤリヤ
三角波形一周期毎のデツドタイムを電流位相の反
転毎と、大幅に減少しようとするもので、以下本
発明を第3図、第4図に示す実施例に基づき具体
的に説明する。 In view of the above, the present invention interrupts the on/off command of the main circuit transistor when the anti-parallel connected diode conducts in a state where current is continuously flowing, thereby reducing the power loss of the main circuit transistor and its base drive circuit. The purpose of this invention is to reduce the dead time for each cycle of the carrier triangular waveform and to significantly reduce the dead time for each cycle of the carrier triangular waveform for each reversal of the current phase. Explain.
第3図において、17,18,19が本発明に
係る回路で、電流指令Iの極性を判別して、トラ
ンジスタを選択する主回路トランジスタ選択回路
と、インバータ出力電圧指令のキヤリヤ波形と比
較して得たパルス波形を上記トランジスタ選択指
令と論理積演算を行うANDゲート、を新たに挿
入したもので、その余の構成は従来例と均等で同
一符号で示した。 In FIG. 3, 17, 18, and 19 are circuits according to the present invention, which compare the main circuit transistor selection circuit that discriminates the polarity of the current command I and selects a transistor with the carrier waveform of the inverter output voltage command. The obtained pulse waveform is newly inserted with the above-mentioned transistor selection command and an AND gate that performs an AND operation.The rest of the configuration is the same as the conventional example and is indicated by the same reference numerals.
すなわち、この発明は正弦波電流指令Iの極性
を、若干の立上り遅れを有しタイムラグを備えた
矩形波形として検出し、これをトランジスタオ
ン、オフの実際のパルス波形に比較、論理積演算
を行い、電流通路になるトランジスタのみにオ
ン/オ不指令を与え、他方分岐のトランジスタは
オフ指令となし、逆並列接続ダイオードの導通時
に同一分岐トランジスタの導通を阻止したことを
特徴とする。 That is, the present invention detects the polarity of the sine wave current command I as a rectangular waveform with a slight rise delay and a time lag, compares this with the actual pulse waveform of the transistor on and off, and performs an AND operation. The present invention is characterized in that ON/OFF commands are given only to the transistors forming the current path, and OFF commands are given to the transistors in the other branch, thereby preventing conduction of the transistors in the same branch when the anti-parallel connected diodes are conductive.
第4図はタイムチヤートにより説明すると、電
流指令Iは、トランジスタ選択回路17により、
その立上りに若干のタイムラグを設けた正・負極
性に対応する矩形波e1,e2に変換され、かつ一方
電流指令Iと電流帰還信号Ifとが比較、電流調節
器1を介して得られた電圧指令bの、キヤリヤ三
角波aとの比較結果であるトランジスタオン/オ
フ指令のパルス波形Cを得る。このパルス波形C
及び反転波形と先の電流極性に対応の矩形波e1,
e2との論理積演算を行ない、得られた電流極性に
応じたパルス波形f1,f2を各分岐のトランジスタ
3,4のオン/オフ指令となし、その結果、上下
トランジスタの一方3がオン、オフされている
間、他方分岐トランジスタ4はオフのままであ
り、負荷電流はトランジスタ3とダイオード1
2、及びトランジスタ4とダイオード11、の各
組合せにより、正負極性に応じて流れることにな
る。 4 is a time chart, the current command I is set by the transistor selection circuit 17,
It is converted into rectangular waves e 1 and e 2 corresponding to positive and negative polarities with a slight time lag in its rise, and on the other hand, the current command I and the current feedback signal If are compared and obtained via the current regulator 1. A pulse waveform C of a transistor on/off command is obtained as a result of comparing the voltage command b with the carrier triangular wave a. This pulse waveform C
and the inverted waveform and the square wave e 1 corresponding to the previous current polarity,
The AND operation with e 2 is performed, and the pulse waveforms f 1 and f 2 corresponding to the obtained current polarity are used as on/off commands for transistors 3 and 4 of each branch, and as a result, one of the upper and lower transistors 3 is turned on. While being turned on and off, the other branch transistor 4 remains off, and the load current flows between transistor 3 and diode 1.
2, and each combination of the transistor 4 and the diode 11 causes the current to flow depending on the positive or negative polarity.
電流指令の極性に対応のパルス波形e1,e2は、
その立上りにタイムラグを設け若干のデツドタイ
ムを生じるようにしているが、もちろんこれは従
来例におけるキヤリヤ三角波の半周期毎にデツド
タイムを設けたこと、と均等であり、上下トラン
ジスタ3,4の短絡を防ぐためにあり、電流の極
性が反転し上下トランジスタの一方から他方へ切
替わる際、トランジスタの双方が共に導通状態に
なり電源短絡となるのを防ぐものである。 The pulse waveforms e 1 and e 2 corresponding to the polarity of the current command are:
A time lag is provided at the rise of the signal to create a slight dead time, but this is of course equivalent to providing a dead time for every half period of the carrier triangular wave in the conventional example, and prevents a short circuit between the upper and lower transistors 3 and 4. This is to prevent both transistors from becoming conductive and shorting the power supply when the polarity of the current is reversed and switched from one of the upper and lower transistors to the other.
このように、正弦波PWM制御トランジスタイ
ンバータにあつて、従来は、キヤリヤ三角波の半
周期毎にデツドタイムを必要とし、そのため種々
悪影響を及ぼしていたが、この発明は、逆並列接
続ダイオードの導通の間、そのトランジスタへの
ベース入力は与えないようにして、上下トランジ
スタの一方のトランジスタをオン、オフのパルス
幅制御し、他方トランジスタをオフのままとした
もので、更に上下トランジスタを切替える正弦波
電流指令位相反転時に、先のキヤリヤ三角波の半
周間毎のデツドタイムと同様の、一方のトランジ
スタが完全にオフしたことを確認して後他方トラ
ンジスタをオンとする電源短絡回避のためのタイ
ムラグ、を設けたことを特徴とするものでダイオ
ードが励起の間並列トランジスタのオン、オフは
何ら機能に関係ないことに着目し、この間のベー
ス入力の生成を停止したこと、であり、この種正
弦波PWM制御トランジスタインバータにあつ
て、懸案となつていたデツドタイムに起因する
種々の不具合、例えばインバータ出力電圧、電流
が同一極性の間で出力電圧より一定値電圧を引き
去り、逆に反対極性の間で足し込む作用をなし極
性モードにより反対の働きをなし非対称に影響を
及ぼすとか、同様の理由で力率が1近くであれば
出力電圧は常に指令値より低く現われ最大出力電
圧の低下を招く等、の問題を解消することができ
るという優れた特長を有する。 As described above, in the conventional sine wave PWM controlled transistor inverter, a dead time is required for every half period of the carrier triangular wave, which has various negative effects. , without applying the base input to that transistor, the pulse width of one of the upper and lower transistors is controlled to turn on and off, and the other transistor remains off, and the sine wave current command is used to switch the upper and lower transistors. At the time of phase inversion, a time lag is provided to avoid a power supply short circuit by confirming that one transistor is completely turned off and then turning on the other transistor, similar to the dead time for each half period of the carrier triangular wave. This type of sine wave PWM controlled transistor inverter focuses on the fact that the on/off state of the parallel transistors has no relation to the function while the diode is excited, and stops generating the base input during this period. In this case, various problems caused by dead time have been a concern, such as removing a constant voltage from the output voltage when the inverter output voltage and current are of the same polarity, and conversely adding it when the inverter output voltage and current are of the opposite polarity. This solves problems such as polarity modes having opposite effects and asymmetrical effects, and for similar reasons, if the power factor is close to 1, the output voltage always appears lower than the command value, resulting in a decrease in the maximum output voltage. It has the excellent feature of being able to
図面は、第1図が従来の正弦波PWM制御トラ
ンジスタインバータの一相分ブロツク図、第2図
がその動作説明のためのタイムチヤート、第3図
が本発明実施例のブロツク図、第4図が同じく動
作説明のタイムチヤート、である。
1…電流調節器、2…比較器、3…上トランジ
スタ、4…下トランジスタ、7…発振器、17…
トランジスタ選択回路、18…ANDゲート、1
9…ANDゲート。
In the drawings, Fig. 1 is a one-phase block diagram of a conventional sine wave PWM control transistor inverter, Fig. 2 is a time chart for explaining its operation, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4. This is also a time chart explaining the operation. DESCRIPTION OF SYMBOLS 1... Current regulator, 2... Comparator, 3... Upper transistor, 4... Lower transistor, 7... Oscillator, 17...
Transistor selection circuit, 18...AND gate, 1
9...AND gate.
Claims (1)
て、速度・トルク制御を行う正弦波PWM制御の
トランジスタインバータにおいて、電流指令の正
負極性に応じて矩形波を生成しかつその矩形波立
上りにタイムラグを持たせたトランジスタ選択回
路と、電流調節器の電圧指令と発振器のキヤリヤ
三角波を比較し上下トランジスタのオン/オフ制
御用パルス波形を出力する比較器と、比較器のパ
ルス波形及びその反転波形と上記トランジスタ選
択回路の矩形波とを論理積演算するANDゲート、
を備え、電動機電流の正負極性に対応して上下ト
ランジスタの一方をオン/オフ制御し、他方のト
ランジスタをオフのままとしたことを特徴とする
正弦波PWM制御トランジスタインバータ。1 In a sine wave PWM controlled transistor inverter that has a current control loop and adjusts the sine wave current to control speed and torque, it generates a rectangular wave according to the positive or negative polarity of the current command, and there is a time lag in the rise of the rectangular wave. a transistor selection circuit with an AND gate that performs an AND operation with the rectangular wave of the transistor selection circuit;
A sine wave PWM control transistor inverter characterized in that one of the upper and lower transistors is controlled on/off in response to the positive and negative polarities of the motor current, while the other transistor remains off.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59010597A JPS60156280A (en) | 1984-01-23 | 1984-01-23 | Sinusoidal pwm control transistor inverter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59010597A JPS60156280A (en) | 1984-01-23 | 1984-01-23 | Sinusoidal pwm control transistor inverter |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60156280A JPS60156280A (en) | 1985-08-16 |
JPH0446073B2 true JPH0446073B2 (en) | 1992-07-28 |
Family
ID=11754648
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59010597A Granted JPS60156280A (en) | 1984-01-23 | 1984-01-23 | Sinusoidal pwm control transistor inverter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60156280A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001309690A (en) * | 2000-04-19 | 2001-11-02 | Denso Corp | Drive device of electric load |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62290361A (en) * | 1986-06-06 | 1987-12-17 | Fuji Electric Co Ltd | Control system for pulse-width modulation control inverter |
YU49125B (en) * | 1999-06-29 | 2004-03-12 | Milan Dr. Prokin | Bridge amplifier with voltage lifter |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57180377A (en) * | 1981-04-28 | 1982-11-06 | Toshiba Corp | Controller for inverter |
-
1984
- 1984-01-23 JP JP59010597A patent/JPS60156280A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57180377A (en) * | 1981-04-28 | 1982-11-06 | Toshiba Corp | Controller for inverter |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001309690A (en) * | 2000-04-19 | 2001-11-02 | Denso Corp | Drive device of electric load |
Also Published As
Publication number | Publication date |
---|---|
JPS60156280A (en) | 1985-08-16 |
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