JPS63226958A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a highly reliable device whose write yield rate is high by a method wherein an electric conductor film and a metal electrode are made conductive by breaking a high-resistance film and the information is written so that the high integration density of a memory element can be realized by reducing the area occupied by a unit memory element and that the parasitic thyristor effect between memory element can be prevented. CONSTITUTION:A unit memory element is constituted by the following: a buried layer 12, of an opposite conductivity type, formed selectively on a semiconductor substrate 11 of one conductivity type; a semiconductor layer 14 formed on the layer; a silicide region 16 which contains a Schottky junction formed on the surface of the semiconductor layer 14; an electric conductor layer 16, a highresistance film 19 and a metal electrode 20 which are formed in succession on the silicide region 16. For example, said high-resistance film 19 is composed of high-resistance polycrystalline silicon, and the silicide region 16 is composed of platinum silicide. The information is written into this unit memory element in the following sequence: the unit memory element is selected by using the metal electrode 20 and the N<+> buried layer 12; a write electric current is supplied from the metal electrode 20; the high-resistance polycrystalline silicon film 19 is broken by a spike caused by a reaction of the metal electrode 20 with the polycrystalline silicon film 19; the electrical continuity is achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor memory devices, and more particularly to programmable read-only memory elements.

[Conventional technology]

Traditionally, programmable destructive storage devices (P
rogran+able Read 0nly Mem
A junction-destructive FROM has been proposed as a PROM (hereinafter abbreviated as PROM).

FIG. 3 is a cross-sectional view of a unit memory element of a conventional junction breakdown type FROM. 33 are selectively formed, respectively, and an N0 type epitaxial silicon layer 34 is grown thereon. This N-type epitaxial 9937 layer 34 includes silicon oxide 1ilI
35 is selectively formed to electrically isolate between unit memory elements, and in this isolated region of the N-type epitaxial layer 34, a P9-type base region 36 and an N-type base region 36 are formed.

A mold emitter region 37 is sequentially formed. This N-type emitter region 37 is wired in a negative column by an aluminum electrode 38 to form a digit line.

Writing of information in this memory element is performed by destroying the PN junction between the emitter and base of the selected unit memory element. That is, as shown in FIG. 4, the memory element Q10 to be written is connected to the digit line D0 and the word line W1.
and then write current I- from digit line D0.
Flow and absorb from word vAw +. This results in
Write current ■8 passes through current path A, unit storage element Q,
. The PN junction between the emitter and base of is destroyed, and the unit storage element Q1° is written.

[Problem that the invention seeks to solve]

The conventional memory element structure described above has a P′-type base region 36.
Since the N-type emitter region 37 is formed inside the
The area occupied by a unit memory element light is limited to the emitter region 37, making it difficult to achieve high integration of the memory element.

In addition, with the demand for faster FROM, it has become necessary to reduce the thickness of the N-type epitaxial silicon layer 34 in order to improve the cutoff frequency f of the peripheral circuit. Similarly, when forming a thin N'' type epitaxial silicon layer, the width of the P'' type base region 36 of the memory element becomes relatively narrow, resulting in the following two problems.

One is that as the width of the base region becomes narrower, the current amplification factor hFE increases, a parasitic thyristor effect (parasitic PNPN effect) occurs between storage elements, and a write failure occurs. This phenomenon, as shown in FIG. When a written storage element Q0° exists on the same digit line D0, a parasitic thyristor Q is generated between this base region and the adjacent unwritten storage element Q01.

Therefore, when the current amplification factor of the storage element is high, this parasitic thyristor Q3 operates, and part or all of the write current (8) that should flow through the current path A flows through the parasitic thyristor Q.

The current flows through the current path B through the written storage element Q. Therefore, the unwritten storage element Q, into which information is to be written. This is a problem where information is not written or is written insufficiently.

Another problem is that the width of the base region of the memory element is relatively narrow, so when destroying the emitter-base junction in order to write information into the unit memory element, there is a risk of also destroying the base-collector junction. This is a problem that causes a decrease in write yield.

The present invention reduces the area occupied by a unit memory element to enable higher density of memory elements, and prevents parasitic thyristor effects between memory elements, thereby achieving a high reliability semiconductor memory device with high write yield. is intended to provide.

[Means for solving problems]

A semiconductor memory device of the present invention includes: a buried layer of an opposite conductivity type selectively formed on a semiconductor substrate of one conductivity type; a semiconductor layer thereon; a silicide region having a Schottky junction formed on the surface of the semiconductor layer; A conductor layer, a high-resistance film, and a metal electrode formed sequentially on this silicide region constitute a unit memory element, and by breaking this high-resistance film, the conductor film and the metal electrode are electrically connected to write information. The structure is such that it is possible to do this.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of a FROM memory element which is an embodiment of the present invention.

Here, N is placed on the P-type semiconductor substrate 11 as a word line.
A '-type buried layer 12 and a P'-type buried layer 1113 for element isolation are selectively formed, respectively, and an N-type epitaxial 9932 layer 14 is grown on the P-type semiconductor substrate 11 in the parentheses. A silicon oxide film 15 is selectively formed on this N-type epitaxial 9932 layer 14, and by reaching the P''-type buried layer 13, unit storage elements are electrically isolated.

A silicon oxide film 17 is formed on the surface of the N-type epitaxial 9932 layer 14 separated by the silicon oxide film 15, and an opening is formed by selectively etching the silicon oxide film 17. For example, a platinum silicide region 16 is formed on the surface of the N-type epitaxial 9932 layer 14 exposed in this opening. Further, a conductive layer 18 made of a metal such as titanium or titanium tungsten is formed to cover this opening, and a high-resistance polycrystalline silicon layer 19 is further formed to cover this conductive layer 18. do. On this high-resistance polycrystalline silicon layer 19, a metal electrode 20 made of aluminum or the like is formed as a digit line.

Therefore, in the FROM having this configuration, since the platinum silicide region 16 is formed on the surface of the N-type epitaxial 9937 layer 14, the unit memory element is configured as a Schottky barrier diode (SBD) structure.

To write information to this unit memory element, a unit memory element is selected using the metal electrode 20 and the N buried layer 12, and then a write current is applied from the metal electrode 20 to the metal electrode 20.
A spike formed by the reaction between the high-resistance polycrystalline silicon 19 and the polycrystalline silicon 19 breaks down the high-resistance polycrystalline silicon 19 and makes it conductive, thereby performing writing.

Therefore, when comparing this embodiment with the conventional structure shown in FIG.
Conventionally, since both the P'-type base region and the N3 emitter region are composed of diffusion layers, the occupied area per unit memory element needs to be 10 μm, but in this embodiment, an SBD is formed on the surface of the N-type epitaxial 9937 layer 14. Because of this structure, the area occupied by each unit memory element can be reduced to 4 μmQ, which is significantly smaller than in the past, and the density of the memory elements can be increased.

Furthermore, in this embodiment, unlike the conventional junction transistor structure, the memory element has only one SBD structure as a junction, so a parasitic thyristor effect does not occur between the memory elements, and normal writing is possible. This makes it possible to obtain a highly reliable memory element.

On the other hand, spikes that occur in the polycrystalline silicon 19 when writing information are caused by the conductor layer 1 provided under the polycrystalline silicon 19.
8 prevents the metal from reaching the platinum silicide region 16. Therefore, destruction of the SBD junction can be prevented, and there is no reduction in write yield.

Furthermore, according to the present invention, the platinum silicide region 16 formed on the N-type epitaxial 9937 layer 14 is extremely thin (approximately 300 layers), and therefore can sufficiently withstand the demands for a thin N-type epitaxial silicon layer due to the structure of peripheral circuits. obtain. For example, in conventional unit memory elements, the epitaxial silicon layer needs to have a thickness of 3.0 μm or more, but according to the present invention, it functions satisfactorily even with a thickness of 1.0 μm or less.

Therefore, the memory element does not affect the thickness of the epitaxial silicon layer at all, and it is possible to sufficiently withstand demands for higher speeds.

FIG. 2 is a cross-sectional view of another embodiment of the present invention, and the same parts as in the previous embodiment are given the same reference numerals and detailed explanations will be omitted.

This embodiment differs from the previous embodiment in that a P' type diffusion region 21 is provided under the boundary between the platinum silicide region 1G and the silicon oxide film 17. According to this structure, it is possible to obtain the same effect as in the embodiment described above, and by providing the P4 type diffusion region 21, the electrical characteristics of the SBD junction are improved compared to the structure in the embodiment described above. It is also possible to obtain the effect of stabilizing.

The conductive layer 18 is made of a material having barrier properties against spikes, such as titanium tungsten.

A high melting point metal such as titanium nitride is preferred. Further, the high-resistance polycrystalline silicon layer 19 may be composed of an insulating film.

〔Effect of the invention〕

As explained above, the present invention selectively forms a Schottky junction silicide region on a semiconductor substrate, and forms a unit memory element by sequentially forming a conductor layer, a high resistance film, and a metal electrode on this silicide region. Therefore, by destroying this high-resistance film, the conductor film and the metal electrode can be electrically connected and information can be written. Therefore, the occupied area per unit memory element is reduced, and it becomes possible to increase the density of memory elements. In addition, there is no parasitic thyristor effect between the memory elements, and there is no risk of element destruction when writing information.
Since a memory element without deterioration can be obtained, a memory device with high write yield and high reliability can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an embodiment of the semiconductor memory device of the present invention;
FIG. 2 is a sectional view of another embodiment of the present invention, FIG. 3 is a sectional view of a conventional structure, and FIG. 4 is an equivalent circuit diagram for explaining the problems of the conventional structure. 11...P type semiconductor substrate, 12...N'' type buried layer,
13... P buried layer, 14... N-type epitaxial silicon layer, 15... silicon oxide film, 16... platinum silicide region, F... silicon oxide film, 18...
...Conductor layer, 19...High resistance polycrystalline silicon layer, 2
0... Aluminum electrode, 21... PI type diffusion region, 31... P type semiconductor substrate, 32... N° type buried layer, 33... P' buried layer, 34... N-type epitaxial silicon layer, 35... silicon oxide film, 36...
P3 type base region, 37...N° type emitter region, 3
8...Aluminum electrode. Figure 1 Figure 2

Claims (4)

[Claims] (1) A buried layer of an opposite conductivity type selectively formed on a semiconductor substrate of one conductivity type, a semiconductor layer formed thereon, a silicide region having a Schottky junction formed on the surface of this semiconductor layer, and this silicide region A semiconductor memory device characterized in that a unit memory element is constituted by a conductor layer, a high resistance film, and a metal electrode that are sequentially formed on the top. (2) The semiconductor memory device according to claim 1, wherein the high resistance film is high resistance polycrystalline silicon or an insulating film. (3) The semiconductor memory device according to claim 1, wherein the silicide region is made of platinum silicide. (4) The semiconductor memory device according to claim 1, wherein the conductive layer is made of titanium tungsten or titanium nitride.