JPH0368537B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to the structure of a resistive element formed therein.

A semiconductor integrated circuit device (hereinafter referred to as IC) is
Active elements such as transistor elements and diode elements, and passive elements such as resistive elements and capacitor elements are built on a single semiconductor substrate, and these are interconnected to realize a circuit function. From the viewpoint of the manufacturing process, the active and passive elements described above are formed in the same manufacturing process as the transistor element.

That is, as shown in FIGS. 1 to 3 showing the manufacturing process when the emitter resistor element of an NPN transistor is connected, first a P-type silicon substrate 1 is prepared, and a highly concentrated N ⁺ diffusion region is formed on the surface of the P-type silicon substrate 1. 2 is selectively formed, and an N-type epitaxial silicon layer 3 is grown on the silicon substrate 1 (FIG. 1).
This region 2 is for reducing the collector series resistance of the NPN transistor 2.

Next, as shown in FIG.
A high concentration of P ⁺ that electrically insulates the transistor element and the resistance element reaches the substrate 1 from the surface of
A type of insulation isolation diffusion region 4 is formed and the epitaxial layer 3 is formed with a region 3a forming a low resistivity resistor.
It is electrically isolated into a region 3b where an NPN transistor is formed. Next, a P-type diffusion region 5b, which will become the base region of the NPN transistor, is formed on the surface of the epitaxial layer in region 3b, and at the same time, a region functioning as a resistance region is formed on the surface of the epitaxial layer in region 3a. A P-type diffusion region 5a is formed for electrical isolation from the resistor element. and,
A high concentration N + diffusion region 6b is formed on the surface of the P-type diffusion region 5b to become the emitter region of the NPN transistor, and at the same time a high concentration N ⁺ diffusion region 6b is formed on the surface of the epitaxial layer of the region 3b to become the collector contact region of the NPN transistor ^. On the surfaces of the diffusion region 6c and the P-type diffusion layer 5a, high-concentration N ⁺ diffusion regions 6a, which serve as resistance regions with low resistivity, are formed.

Next, as shown in FIG. 3, a silicon oxide film 7 is formed on the entire surface to insulate the aluminum wiring, holes are formed in the silicon oxide film 7 at locations where electrodes will be formed, and aluminum is deposited on the entire surface, and then selected. By etching the electrodes 8a, 8b,
8c and 8d are formed. Electrode 8b is resistance region 6a
one end and the emitter region 6b of the NPN transistor
is connected to. That is, the resistance region 6a is used as an emitter resistance of the transistor.
Since this region (N-type) 6a is formed in and in contact with the P-type region 5a, the region 6a and the region 5
A and a form a PN junction, that is, a parasitic diode.

In this way, the resistive element is simultaneously formed using the transistor diffusion process, and no special manufacturing process is required to form the resistive element. However, on the other hand, if a sudden abnormal voltage such as a surge or spike due to static electricity is applied from the outside to the electrode 8a, the PN junction formed by the base region 5b and emitter region 6b of the NPN transistor In terms of resistivity, P-type diffusion region 5a and high concentration N ⁺ diffusion region 6
The reverse breakdown voltages of both regions with respect to the PN junction formed by a are approximately equal because each region is formed in the same process. For this reason, there was a drawback that the PN junction between the base and emitter of the NPN transistor following the low resistivity resistor deteriorated or was destroyed.

Therefore, it is an object of the present invention to prevent the deterioration or destruction of the PN junction between the base and emitter of the transistor following the low resistivity resistor even if an external surge caused by static electricity or a sudden abnormal potential such as spice is input. An object of the present invention is to provide a semiconductor integrated circuit device that does not cause this problem.

The present invention forms an impurity region of one conductivity type in a semiconductor base layer of an opposite conductivity type grown on a semiconductor substrate of one conductivity type, the surface impurity concentration of which is higher than the surface impurity concentration of the base region of a transistor element, An opposite conductivity type region is formed in this high surface impurity concentration region at the same time as the emitter region of the transistor element, and a resistance region formed of this opposite conductivity type region is connected to the emitter region.

In this case, the high surface impurity concentration region is preferably an insulating isolation region of one conductivity type provided to isolate the transistor element from another transistor element or another element.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings.

4 to 6 are cross-sectional views showing the manufacturing process of a low resistivity transistor and an NPN transistor connected thereto according to an embodiment of the present invention.

First, as shown in FIG.
A well-known photoresistor process and a diffusion process are performed on the surface of the substrate to form a high concentration N ⁺ -type diffusion region 10 in a portion where an NPN transistor is to be formed. This is to reduce the collector series resistance of the transistor. Thereafter, an N-type silicon epitaxial layer 11 is grown on the silicon substrate 9.

Next, as shown in FIG.
In step 1, a high concentration P ^{+ type insulation isolation diffusion region 12a for electrically isolating each element is formed on the entire region where a low resistivity resistor is to be formed until reaching the silicon substrate 9, and at the same time, a high concentration P +} type insulation isolation diffusion region 12a is formed on the silicon substrate 9. A high concentration P ⁺ -type insulation isolation diffusion region 12b is formed to isolate the epitaxial layer 11a in the region where the NPN transistor is to be formed from other elements. Then, on the surface of the epitaxial layer 11a, a P-type diffusion layer 13b is formed which becomes the base region of the NPN transistor.
At the same time, a resistive region is formed on the surface of the insulation isolation diffusion region 12a, which will be explained in detail later.
P to make the reverse yield characteristic of PN junction steep
A type diffusion layer 13a is formed.

Thereafter, as shown in FIG. 6, an emitter region 14b formed by a high concentration N ⁺ diffusion layer is formed according to a well-known diffusion process.
After forming a collector contact region 14c and a low resistivity resistance region 14a, forming a silicon oxide film 15 on the entire surface and opening a hole in a predetermined portion, a metal such as aluminum is deposited and selectively etched away to form an electrode. Aluminum wiring 16 is formed.

In the semiconductor integrated circuit device of this embodiment, the resistance region 14a is formed within the insulation isolation region 12a. This insulating isolation region 12a has an extremely high impurity concentration in order to reliably electrically insulate transistor elements, resistance elements, and the like. On the other hand, the impurity concentration of base region 13b is considerably lower than that of insulating isolation region 12a. As is known, the breakdown voltage of a PN junction is determined by the impurity concentration of the P region and the N region, and the higher the concentration, the lower the breakdown voltage. Therefore, the breakdown voltage of the PN junction formed in the resistance element is smaller than that of the base-emitter PN junction of the transistor element. Therefore, even if an abnormal voltage such as static electricity is input from the outside to the electrode 16 of the resistance element, the PN junction of the resistance element breaks down earlier than the base-emitter PN junction of the transistor element, and the voltage is applied to the resistance region 14a. The abnormal charge is caused to flow to the region 13a. In this case, area 13a and area 12
Since a is in the forward direction, the abnormal charge in the resistance region 14a is discharged to the substrate 9 via the regions 13a and 12a. As an example, regions 14a and 13a
The breakdown voltage of the PN junction formed by is 5.9V, region 1
4b, the breakdown voltage of the PN junction formed in region 13b is 6.5V. Therefore, the aluminum wiring 1 connecting one end of the resistance element and the emitter region 14b
The potential of No. 6 is maintained at the breakdown voltage of the PN junction of the resistive element, and there is no deterioration or destruction of the base-emitter junction as in the conventional case.

In this way, such a semiconductor integrated circuit device can protect the transistors from static electricity applied from the outside, and can provide extremely reliable static electricity withstand voltage. When a transistor region breaks down, the HFE of the transistor decreases, but in a resistor, characteristics do not deteriorate unless a large current flows, so a small-energy surge voltage will not cause the resistor to break down. However, if enough energy is applied to destroy the resistor, it is thought that the transistor will also be affected.

Incidentally, in this embodiment, the region 13a was formed in the insulation isolation region 12a of the portion where the resistance element was to be formed when the base region 13b of the transistor element was formed. However, this region 13a is a resistive element.
This is not necessarily necessary from the viewpoint of making the breakdown voltage of the PN junction smaller than that of the PN junction between the base and emitter of the transistor element. Further, from the same viewpoint, the resistance region 14a may be formed in a region having a higher surface impurity concentration than the base region 13b, instead of forming the resistance region 14a in the insulating isolation region 12a.

However, in the latter case, an extra manufacturing process is required, which hinders cost reduction.
Furthermore, an isolation region is required to insulate the resistance element from other elements, which also reduces element density.
Therefore, in this embodiment, the insulation isolation region 12a also serves to lower the breakdown voltage and isolate the elements, thereby reducing the cost and increasing the element density.

In the former case, as described above, the impurity concentration of the insulating isolation region 12a is extremely high, and since the resistance region 14a is also formed at the same time as the emitter region 14b, its impurity concentration is also high. Therefore, the impurity concentration near the surface of the resistance element is extremely high, resulting in deterioration of characteristics such as an increase in surface lease current. For this reason, a region 13a is formed in the insulating isolation region 12a at the same time as the base region is formed. That is, after forming region 13a, an insulator required to form region 14a must be formed. For this insulator, a method is usually used in which silicon on the surface is converted to silicon dioxide by heat treatment in an oxidizing atmosphere. Therefore, area 13
The surface of a is oxidized, and the surface impurity concentration in the vicinity of the region that forms a junction with region 14a is reduced, so that the leakage current no longer increases, and the breakdown of the PN junction becomes steeper, so that the transistor is more reliably protected. Ru. Furthermore, the time required to form the diffusion mask for forming the region 14a is significantly shortened because the oxide film on the region 13a only needs to be removed.

Although the base forming step is used in this embodiment as a means for reducing the surface impurity concentration of the insulation isolation region 12a, the same effect can be achieved by adding a new heat treatment step for forming an oxide film. However, considering the increase in manufacturing steps as described above, this embodiment is far superior as it only requires changing the shape of the mask when forming the base.

Further, in the semiconductor integrated circuit device of this embodiment, an aluminum wiring 16b is formed on the insulating layer 15 on the low resistance region 14a. Rather than using multilayer wiring technology to form aluminum wiring on both sides of the intersecting aluminum wiring, this resistor element uses a low-resistivity semiconductor region for one aluminum wiring, and the crossing portion is made of semiconductor. This is used as a so-called tunnel resistor formed within the base (epitaxial layer 11). That is, the electrode 16a and the aluminum wiring 16c are originally continuous, and the wiring 16a, 16c and the wiring 16
It intersects with b. Therefore, instead of crossing both wirings using multilayer wiring technology, the electrode 16a and the wiring 16c are connected using the low resistance region 14a as a tunnel resistance, thereby achieving the same function as the multilayer wiring. However, it goes without saying that the invention may also be applied to ordinary resistance elements.

As described above, the semiconductor integrated circuit device of this embodiment can prevent destruction of transistors due to external static electricity, etc., without increasing the number of manufacturing steps or causing characteristic deterioration.

Note that the present invention is not limited to the above embodiments, and all conductive types may be replaced. Further, although the insulating film 15 is newly formed before forming each electrode, the insulating film used when forming each region may be left as is. Furthermore, it goes without saying that the materials of the insulating film and the metal wiring are not limited to these. Further, the insulating regions 12a and 12b were formed until they reached the substrate 9, but a new P ⁺ type buried layer was previously formed on the substrate 9, and the insulating regions 12a and 12b were
It may be made continuous with 2b to form an insulating region.

[Brief explanation of drawings]

1 to 3 are cross-sectional views of the manufacturing process of a conventional semiconductor integrated circuit device, and FIGS. 4 to 6 are cross-sectional views of the manufacturing process of a semiconductor integrated circuit device showing an embodiment of the present invention. 1, 9... P-type silicon substrate, 2, 10...
N ⁺ type buried layer, 3, 11...N type epitaxial layer, 4, 12a, 12b...P ⁺ type insulation isolation region, 5b, 13b...P type base region, 5a, 1
3a...P-type region for insulating resistance region, 6b,
14b...N ⁺ type emitter region, 6a, 14a...
...Resistance region, 7, 15...Insulating layer, 8a to 8
d, 16a to 16e...metal wiring layers.

Claims (1)

[Claims] 1. A transistor element having a semiconductor base layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, and having a base region of one conductivity type and an emitter region of the opposite conductivity type on this semiconductor base layer. In the semiconductor integrated circuit device, the semiconductor base layer has an impurity region of one conductivity type whose surface impurity concentration is higher than that of the base region, and the emitter region and the high surface impurity concentration region are provided. 1. A semiconductor integrated circuit device comprising regions of opposite conductivity type having the same impurity concentration, and a resistance region formed of the regions of opposite conductivity type being electrically connected to the emitter region. 2. The semiconductor integrated circuit device according to claim 1, wherein the high surface impurity concentration region is an insulating isolation region.