JPS629663A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make the area small and to prevent a parasitic thyristor from being created, by biasing the substrate to the ground potential and the second island region to a potential higher than the ground potential. CONSTITUTION:A diode and an NPN transistor having a collector with a negative potential against the substrate, are connected so that the cathode 12 corresponds electrically to the collector 10 and the anode 9 to the substrate 1 (insulating separation region). Since the diode can be shielded by the N region 13 which can be made a high potential against the substrate, a parasitic thyristor can not be created. That is, when the collector potential of the NPN transistor falls below the substrate potential, the forward voltage of the diode can clamp the negative potential. Moreover, when a diode with a small forward voltage is used, the diode shoulders much of the current caused by insulation breakdown resulting from the applied negative potential. Accordingly, the alphaof a parasitic NPN transistor consisting of an apparent NPN transistor can be lowered, so the parasitic transistor can be prevented from being created.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and more particularly to parasitic PNPN that occurs when a potential lower than the substrate potential of an IC is applied to an N-type semiconductor region. The present invention relates to a protection element that prevents the occurrence of thyristors.

[Conventional technology]

Conventionally, as a means to prevent the occurrence of this type of parasitic PNPN thyristor, the average distance between various junctions has been increased in order to reduce the current amplification factor (α) of the parasitic NPN) transistor and PNP) transistor that constitute the parasitic PNPN thyristor. Or, a dummy NPN transistor was intentionally installed to reduce the α of the undesirable parasitic NPN transistor.

Specifically, in the circuit configuration shown in Fig. 4, other circuits are connected to a transistor TRA whose collector is externally exposed to an output terminal, and in this circuit, for example, a resistor RA and a transistor TRB are present. Assume that the layout is as shown in FIG. 5(a), φ).

Figure 5 (
In case a), there are parasitic NPN transistors such as tra and tra' across the isolation region 106, and t between RA and TRB and the isolation region 106.
A parasitic PNP (parasitic PNP) laser register such as rb, trb' is constructed. In this state, when a voltage lower than the insulating isolation region 106 (biased to the ground potential) is applied to the collector of TRA, tra.

tra' is activated and then each (tra, trb
).

The thyristor (tra', trb') is activated, and TRB and RA cannot operate normally.

In FIGS. 5(a) and 5(b), 101 is a P-type substrate, 102 is an insulator, 103 is an N-type buried layer, and 104 is a P-type substrate.
A mold embedding layer, 107 is an insulated isolation electrode region, 108 is a paste, 110 is a collector, 111 is an emitter, and 114 is a resistor.

As a countermeasure for these problems, it is necessary to lower the α of the parasitic NPN transistors t r a and t r a' (by increasing the width of the isolation region around the TRA, as shown in Fig. 6 (a),
As shown in the cross-sectional view and plan view of (b), an epitaxial region 205 independent from other circuit elements is installed around the TRA, and its potential is biased to VCC or other suitable potential1. (NPN) transistors to avoid affecting internal circuits.

, In addition, Fig. 6 (a), (b) K > Ite,
201 is a P-type substrate, 202 is an insulator, 203 is an N-type buried layer, 206 is an insulation isolation diffusion region, 208 is a paste, 21
0 is a collector, 211 is an emitter, 213 is an N'' electrode region, and 214 is a resistor.

That is, the operation of this dummy NPN transistor results in a parasitic transistor t r a.

tra' becomes inactive, α decreases, and the generation of a parasitic thyristor formed by other circuit elements and the parasitic NPN transistors tra and tra' is suppressed.

[Problem that the invention seeks to solve]

However, as mentioned above, FIG. 6(a).

In order to install a region consisting of an epitaxial layer and an N-type diffusion region insulated from other elements and TRA around the output transistor TRA shown in (b), the original IC
requires extra area unrelated to its operation. Therefore, the IC area becomes large and the pellet cost increases.
Further, the output transistor is usually a power transistor for current driving, and the area of the element itself is large. Therefore, it is easily understood that providing a region having a constant width around the outer periphery and being insulated and isolated from other elements has the drawback of requiring a larger area.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned conventional drawbacks and to provide a small, low-cost semiconductor device that has a small area and can prevent the generation of parasitic thyristors.

[Means for solving problems]

The semiconductor device of the present invention includes a semiconductor body comprising a semiconductor base of one conductivity type, a single epitaxial layer of an opposite conductivity type formed on the semiconductor base, and a second semiconductor body forming an interface between the epitaxial layer of the semiconductor body and the semiconductor base. a buried layer and a contact region in a surface region of one conductivity type located above the first buried layer and extending to the buried layer; a first island region composed of a first impurity region of an opposite conductivity type existing in a surface region of the epitaxial layer; and a surface of the epitaxial layer and the epitaxial layer communicating with the second buried layer; a second island region made up of a second impurity region of an opposite conductivity type present in the semiconductor device, the first island region serving as a cathode, the semiconductor device having the base body at a ground potential. Furthermore, the second island region can be biased to a higher potential than the ground potential. Further, the contact region and the first buried layer serve as an anode, and a third impurity region of a first conductivity type provided on the surface of the first island region apart from the first buried layer or the contact region Further, a metal side of a Schottky barrier provided on a surface of the first island region apart from the first buried layer can be operated.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to (e) are schematic cross-sectional views shown in order of steps to explain an embodiment of the present invention and its manufacturing method, and FIG. 1(f) is a detailed view of the present invention. This is an explanatory plan view, and a cross-sectional view taken along the X-Y line is equivalent to FIG. 1(e).

First, as shown in FIG. 1(a), an opening is formed in the insulator 2 using a specific resistance 1 to 10 technique), and an impurity concentration sufficient to insulate and isolate the P-type buried layer 4 from the substrate 1 is applied. An N-type buried layer 3 having a junction depth is formed. Next, an opening is made at a predetermined position using the same PR technique, and a P-type buried layer and a P-type buried layer are formed.
Form the bottom of the mold isolation region.

Next, as shown in FIG. 1(b), after removing the oxide film 2 and depositing an N-type epitaxial layer 5 having a specific resistance of 1 to 3 Ω and a thickness of approximately 12 μm, an opening is formed at a predetermined position using the PR technique. After that, the upper part of the P-type insulation isolation region 6 is formed from the surface, and the epitaxial layer 5 is separated into each island region.

Next, as shown in FIG. 1C, the P-type insulating isolation electrode region 7, the base region 8 of the output NPN transistor, etc. are formed using the PR technique.

Next, as shown in FIG. 1(d), the collector electrode region 10 of the output NPN transistor is formed by the normal PR technique and the diffusion technique. An emitter region 11.degree. epitaxial region electrode number extrusion regions 12, 13, etc. are formed.

Finally, as shown in FIG. 1(e), metal wiring is formed in each region to complete this embodiment. Further, FIG. 1(f) is a plan view of this embodiment, and its sectional view taken along the line X-Y is equivalent to FIG. 1(e). Note that the same regions are given the same symbols.

A first embodiment of the present invention includes a substrate 1, an insulating isolation region 6. N-type buried layer 3. P-type buried layer 4 and P-type buried electrode extraction region 9 separated from insulating isolation region 6 by N-type buried layer
(the anode of the diode), an epitaxial layer and its electrode region 13 surrounded by the anode and connected to the epitaxial layer and electrode region 12 (the cathode of the diode) and the N-type buried layer. Collector 3, 5, 10.
Pace 8. When a potential lower than the substrate potential (usually the lowest potential) is applied to the collector of the output transistor consisting of the emitter 11, the collector and the substrate are forward biased, forming a parasitic NPN transistor between the epitaxial layer of another element. The cathode 12 of the aforementioned diode according to the present invention is connected to the collector 10 of the output transistor, and the anodes 4 and 9 are connected to the substrate 1.
That is, it communicates with 7 through metal wiring. Furthermore, the N-type region separating the anodes 4, 9 of the diode from the substrate 1 is preferably connected to a high potential. With this configuration, this diode can clamp an applied voltage lower than the ground potential (bottom potential) without causing the cathode 12 to generate a new parasitic thyristor, and can reduce the α of the parasitic NPN transistor, thereby preventing parasitic thyristors. It is sufficiently effective in suppressing the occurrence of thyristors.

FIG. 2 is a sectional view of a second embodiment of the present invention, in which an impurity region 315, which is diffused at the same time as the base 308 of the NPN transistor and the resistor, is used as the anode of the diode. FIG. 3 is a cross-sectional view of a third embodiment of the present invention, which uses a Schottky barrier 416 with a small forward voltage as the anode of the diode, and has a greater ability to suppress the generation of parasitic thyristors with the same area.

Although the embodiments of the present invention have been described above, other regions such as P-type polycrystalline silicon may be provided in contact with the N-type epitaxial layer as the anode of the diode. In addition, although each anode has been made into a single region, it goes without saying that a combination of these may also be used. , cathode 1
2 is connected to the collector 10, and the anode 9 is connected to the substrate 1 (insulating isolation region) so as to be electrically aligned. Since the diode of the present invention can be shielded with the N region 13 that can be made at a high potential with respect to the substrate, the clamp diode itself does not induce a parasitic thyristor as in the conventional case. That is, when the collector of the (NPN) transistor drops below the substrate potential, the forward voltage of the diode can clamp the negative potential without generating a parasitic thyristor together with other circuit elements. t
In addition, when the diode of the present invention with a small forward voltage is used, the diode bears most of the current that flows when the insulation collapses due to the application of a negative potential.
Since it is possible to lower the parasitic thyristor, the generation of parasitic thyristors can be suppressed. Therefore, by using the diode of the present invention (particularly a diode using a Schottky barrier with a small forward voltage and a small area), a large surface area can be used to shield a conventionally used output NPN transistor. This diode is not required and can be installed and connected at any position around the output transistor, increasing the degree of freedom in element layout.

As described above, the present invention makes it possible to prevent the generation of parasitic thyristors in a small area, thereby reducing the cost of IC pellets compared to the conventional method.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(e) are cross-sectional views shown in order of steps to explain the first embodiment of the present invention and its manufacturing method. FIG. 1(f) is a plan view of FIG. 1(e), FIG. 2 is a sectional view of the second embodiment of the present invention, and FIG. 3 is a sectional view of the third embodiment of the present invention. Figure 4 is a schematic diagram of a conventional circuit for preventing the generation of a parasitic PNPN thyristor, Figures 5 (a) and Φ) are explanatory diagrams of the mechanism of parasitic thyristor generation, and Figures 6 (a) and (b).
) are a cross-sectional view and a plan view of a conventional example in which measures have been taken to suppress the parasitic thyristor effect. 1.101,201...P-type substrate, 2,10
2゜202・・・Insulator, 3,103,203・
...N type buried layer, 4,104...P type buried layer, 5.105゜205...Epitaxial layer, 6,106,206...・Insulation isolation diffusion region, 7, 107... Insulation isolation electrode region, 8, 10
8,208,308...Pace, 9...
・P-type buried electrode extraction area, 10, 110, 210-
...Collector, 11,111,211...
・Emitter, 12...Cathode electrode region, 13
, 213...N+ electrode region, 14, 114, 2
14...Resistance, 315...Anode,
416... Schottky barrier. ＼. 2nd mouth 3rd concave GND QND 4th @ Figure S

Claims (5)

[Claims] (1) A semiconductor body consisting of a semiconductor body of one conductivity type and a single epitaxial layer of an opposite conductivity type formed on the semiconductor body, and a semiconductor body formed from the vicinity of the interface between the epitaxial layer of the semiconductor body and the semiconductor body into the epitaxial layer. extends to
and a first buried layer of one conductivity type formed apart from the surface of the epitaxial layer, and a first buried layer extending below the first buried layer and separating the first buried layer from the semiconductor substrate. the first buried layer formed by positioning the contact area in the surface region of one conductivity type above the first buried layer and extending to the first buried layer; a first island region composed of the epitaxial layer existing above and in contact with the epitaxial layer and a first impurity region of an opposite conductivity type existing in the surface region of the epitaxial layer; the epitaxial layer communicating with the second buried layer; and a second island region formed of a second impurity region of an opposite conductivity type existing in a surface region of the epitaxial layer, the first island region serving as a cathode. (2) The semiconductor substrate is biased at a ground potential and the second island region is biased at a potential higher than the ground potential.
1) The semiconductor device described in item 1). (3) A semiconductor device according to claim (1) or (2), in which the contact region and the first buried layer are anodes. (4) Claim (1) or (2) states that the third impurity region of one conductivity type provided on the surface of the first island region apart from the first buried layer is an anode. semiconductor devices. (5) Claim (1) or (2) in which the metal side of the Schottky barrier provided on the surface of the first island region apart from the contact region and the first buried layer is an anode. The semiconductor device described.