JPS63220533A - Mounting structure of ic for clock - Google Patents
Mounting structure of ic for clockInfo
- Publication number
- JPS63220533A JPS63220533A JP5434087A JP5434087A JPS63220533A JP S63220533 A JPS63220533 A JP S63220533A JP 5434087 A JP5434087 A JP 5434087A JP 5434087 A JP5434087 A JP 5434087A JP S63220533 A JPS63220533 A JP S63220533A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- protrusion
- circuit substrate
- circuit board
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000465 moulding Methods 0.000 claims abstract description 7
- 239000004033 plastic Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 8
- 239000000088 plastic resin Substances 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 239000011347 resin Substances 0.000 abstract description 2
- 229920005989 resin Polymers 0.000 abstract description 2
- 229920001187 thermosetting polymer Polymers 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は時計用ＩＣの実装構造に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a mounting structure for a watch IC.
従来のＩＣの実装構造を第２図及び第３図を用いて説明
する。A conventional IC mounting structure will be described with reference to FIGS. 2 and 3.
従来のＩＣの実装方式として、第２図に示す如＜ＩＣチ
ップ１上の素子を保護するパッシベーション膜２の開口
部２ａに設けられたＡｌノくラド１ａ上にＣｒ −Ｃｕ
−Ａ ｕの３層の金属層１ｂを設け、該金属層１ｂを
介して前記Ａｌノ（ラド１ａ上にハンダバンプ６を球状
に形成し、第３図に示す如＜ＩＣチップ１の）１ンダノ
（ンプ６とエポキシ樹脂系の回路基板４のＩＣの配線パ
ターン４ａを対向させ、）・ンダ溶融点以上の熱を加え
ることにより、電気的接続が行われるフェースダウン方
式の実装方式がある。As a conventional IC mounting method, as shown in FIG.
- A three-layer metal layer 1b of Au is provided, and a solder bump 6 is formed in a spherical shape on the rad 1a through the metal layer 1b. There is a face-down mounting method in which electrical connections are made by applying heat above the melting point (by placing the IC wiring pattern 4a of the epoxy resin circuit board 4 facing the amplifier 6 and the IC wiring pattern 4a of the epoxy resin circuit board 4).
これはハンダの表面張力により回路基板４からＩＣチッ
プ１が浮いた状態に保持され、ノ１ンダノくンプ６ａの
弾性力により、温度変化に対して前記回路基板４と前記
ＩＣチップ１の熱膨張率の違いによるストレスを吸収さ
れる役目をしている。This is because the IC chip 1 is held in a floating state from the circuit board 4 by the surface tension of the solder, and due to the elastic force of the solder clamp 6a, the circuit board 4 and the IC chip 1 expand thermally due to temperature changes. Its role is to absorb stress caused by differences in rates.
しかし、このような実装方式においては、ＩＣチップ上
にハンダバンプを成形するための工数がかかる。また、
ＩＣと回路基板とを接続するボンディング工程でのノ１
ンダ溶融点までの加熱温度に充分耐える耐熱性の高いプ
リント基板を使用する必要があり、回路基板が高価なも
のとなってし、まり。However, in such a mounting method, it takes a lot of man-hours to form solder bumps on the IC chip. Also,
No. 1 in the bonding process to connect IC and circuit board
It is necessary to use a highly heat-resistant printed circuit board that can withstand heating temperatures up to the melting point of the semiconductor, making the circuit board expensive.
さらにハンダバンブの大きさ等のバラツキによりボンデ
ィング工程後のＩＣチップと回路基板とのギャップが適
正に確保されない場合には熱影響によるストレスにより
バンプ部分での剥れを起こしたり、或いはＩＣチップと
回路基板のパターンとのショート等が発生し、信頼性の
面で心配な点がある。Furthermore, if the gap between the IC chip and the circuit board after the bonding process is not properly secured due to variations in the size of the solder bumps, the bumps may peel off due to stress caused by heat, or the IC chip and the circuit board may separate. There is a concern about reliability as short-circuits with other patterns may occur.
本発明は以上のような問題を解消させ、ＩＣチップのハ
ンダバンブの廃止によるコストダウン、及び回路基板に
対するＩＣチップの高さ位置の安定化に伴う信頼性の高
いＩＣの実装構造を実現させることを目白りとするもの
である。The present invention solves the above-mentioned problems, reduces costs by eliminating solder bumps on IC chips, and realizes a highly reliable IC mounting structure by stabilizing the height position of the IC chip with respect to the circuit board. It is eye-opening.
ｃ問題点を解決するための手段〕
本発明の構成はプラスチック樹脂成形の回路基板上に一
体成形により突起を設け、ＩＣチップの電極パッドと前
記回路基板の突起の上に導電ペーストにより印刷配線さ
れたパターンと電気的接続が行われる構成となっている
。c. Means for Solving Problems] The structure of the present invention is to provide a protrusion by integral molding on a plastic resin-molded circuit board, and print wiring with conductive paste on the electrode pad of the IC chip and the protrusion on the circuit board. The configuration is such that electrical connections are made with the pattern.
Ｕ下、本発明の一実施例を図面に基ついて説明する。第
１図は本発明の時計用ＩＣの実装＋１４造を示す断面図
である。一体成形により突起５ａを設けたプラスチック
樹脂成形の回路基板５上に導電ペーストをスクリーン印
刷して、前記突起５ａの上面部５１）まで配線パターン
５ｃが形成されている。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a +14 structure in which a watch IC according to the present invention is mounted. A conductive paste is screen printed on a plastic resin-molded circuit board 5 provided with projections 5a by integral molding, and a wiring pattern 5c is formed up to the upper surface portion 51) of the projections 5a.
その際、前記突起５ａの高さく１〕）は段差部５ｄの印
刷性を考慮して４０〜７０ Ｉｔ程度に設定するのが望
ましい。ＩＣチップ６の電極パッド６ａと前記回路基板
５の突起５ａが対応するように回路基板５」二にＩＣチ
ップ６を搭載し、導電ペーストに含まれている熱硬化性
の樹脂イ」が硬化する温度まで加熱することによりボン
ディングが行われ、ＩＣチップ６と回路基板５の突起５
ａ上の配線パターン５Ｃとの電気導１１０が得られる。In this case, it is desirable that the height 1) of the protrusion 5a is set to about 40 to 70 It, taking into consideration the printability of the stepped portion 5d. The IC chip 6 is mounted on the circuit board 5'' so that the electrode pad 6a of the IC chip 6 corresponds to the protrusion 5a of the circuit board 5, and the thermosetting resin contained in the conductive paste is cured. Bonding is performed by heating the IC chip 6 to the protrusion 5 of the circuit board 5.
Electrical conduction 110 with the wiring pattern 5C on a is obtained.
以上の実施例から明らかなように本発明によれば、プラ
スチック樹脂成形の回路基板に一体成形の突起を設ける
ことにより、従来のフェースダウンボンディング実装で
は必要であったＩＣチップのハンダバンブが不要となり
、コストダウンがはかれる。As is clear from the above embodiments, according to the present invention, by providing integrally molded protrusions on a plastic resin molded circuit board, solder bumps for IC chips, which were necessary in conventional face-down bonding mounting, are no longer necessary. Cost reduction can be achieved.
又、回路基板面に対するＩＣチップの高さが一定なので
、基板配線パターンとＩＣチップ下面とのショートを防
止でき、又、突起部がプラスチック樹脂成形部材である
ので、温度変化に対する熱膨張の影響によるＩＣチップ
と回路基板のストレスも緩和することが出来る。又、プ
ラスチック樹脂成形基板の応用として、アナログ水晶時
計の輪列車の軸受穴を一体化成形（図示せず）すること
により、輪列受の兼用化がはがれ大巾なコストダウン効
果の実現が可能である。In addition, since the height of the IC chip relative to the circuit board surface is constant, it is possible to prevent short circuits between the board wiring pattern and the bottom surface of the IC chip, and since the protrusion is a plastic resin molded member, it can be prevented from being affected by thermal expansion due to temperature changes. The stress on the IC chip and circuit board can also be alleviated. In addition, as an application of the plastic resin molded substrate, by integrally molding the bearing hole of the wheel train of an analog quartz clock (not shown), it is possible to make it possible to use it as a wheel train bridge, resulting in a significant cost reduction effect. It is.
第１図は本発明の実施例による時計用ＩＣの実装構造を
示す要部断面図、第２図、第３図は従来のフェースダウ
ンボンディング実装方式のＩＣチップと実装構造を示す
要部断面図である。
１．６・・・・・・ＩＣチップ、
５ａ・・・・・・突起。
５ｃ・・・・・・配線パターン、
６ａ・・・・・・電極パッド。FIG. 1 is a sectional view of a main part showing a mounting structure of a watch IC according to an embodiment of the present invention, and FIGS. 2 and 3 are sectional views of main parts showing an IC chip and mounting structure of a conventional face-down bonding mounting method. It is. 1.6...IC chip, 5a...protrusion. 5c...Wiring pattern, 6a...Electrode pad.
Claims (1)
されたプラスチック樹脂成形の回路基板と、ＩＣの電極
パッドとを電気的に接続する構造において、前記回路基
板上に突起を一体成形により設け、該突起の上に印刷さ
れる前記配線パターンに前記ＩＣの電極パッド部を接続
したことを特徴とする時計用ＩＣの実装構造。In a structure in which a plastic resin-molded circuit board on which a wiring pattern is formed by printing conductive paste and an electrode pad of an IC are electrically connected, a protrusion is integrally formed on the circuit board, and the protrusion is formed on the circuit board by integral molding. A mounting structure for a watch IC, characterized in that an electrode pad portion of the IC is connected to the wiring pattern printed thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5434087A JPS63220533A (en) | 1987-03-10 | 1987-03-10 | Mounting structure of ic for clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5434087A JPS63220533A (en) | 1987-03-10 | 1987-03-10 | Mounting structure of ic for clock |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63220533A true JPS63220533A (en) | 1988-09-13 |
Family
ID=12967875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5434087A Pending JPS63220533A (en) | 1987-03-10 | 1987-03-10 | Mounting structure of ic for clock |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63220533A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02302050A (en) * | 1989-05-16 | 1990-12-14 | Minolta Camera Co Ltd | Ic chip mounting board |
| US5196371A (en) * | 1989-12-18 | 1993-03-23 | Epoxy Technology, Inc. | Flip chip bonding method using electrically conductive polymer bumps |
| EP0817260A3 (en) * | 1996-06-24 | 1998-12-30 | Nec Corporation | IC package, IC prober and connector and method of forming the same |
| US5879761A (en) * | 1989-12-18 | 1999-03-09 | Polymer Flip Chip Corporation | Method for forming electrically conductive polymer interconnects on electrical substrates |
| WO1999063589A1 (en) * | 1998-06-02 | 1999-12-09 | Siemens S.A. | Pad grid array and a method for producing such a pad grid array |
| JP2002324819A (en) * | 2001-04-24 | 2002-11-08 | Matsushita Electric Works Ltd | Ic mounting board and method for manufacturing the same |
| US6518088B1 (en) | 1994-09-23 | 2003-02-11 | Siemens N.V. And Interuniversitair Micro-Electronica Centrum Vzw | Polymer stud grid array |
| US6566149B1 (en) * | 1998-09-16 | 2003-05-20 | Hitachi, Ltd. | Method for manufacturing substrate for inspecting semiconductor device |
-
1987
- 1987-03-10 JP JP5434087A patent/JPS63220533A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02302050A (en) * | 1989-05-16 | 1990-12-14 | Minolta Camera Co Ltd | Ic chip mounting board |
| US5196371A (en) * | 1989-12-18 | 1993-03-23 | Epoxy Technology, Inc. | Flip chip bonding method using electrically conductive polymer bumps |
| US5879761A (en) * | 1989-12-18 | 1999-03-09 | Polymer Flip Chip Corporation | Method for forming electrically conductive polymer interconnects on electrical substrates |
| US5918364A (en) * | 1989-12-18 | 1999-07-06 | Polymer Flip Chip Corporation | Method of forming electrically conductive polymer interconnects on electrical substrates |
| US6138348A (en) * | 1989-12-18 | 2000-10-31 | Polymer Flip Chip Corporation | Method of forming electrically conductive polymer interconnects on electrical substrates |
| US6518088B1 (en) | 1994-09-23 | 2003-02-11 | Siemens N.V. And Interuniversitair Micro-Electronica Centrum Vzw | Polymer stud grid array |
| EP0817260A3 (en) * | 1996-06-24 | 1998-12-30 | Nec Corporation | IC package, IC prober and connector and method of forming the same |
| US5936845A (en) * | 1996-06-24 | 1999-08-10 | Nec Corporation | IC package and IC probe card with organic substrate |
| WO1999063589A1 (en) * | 1998-06-02 | 1999-12-09 | Siemens S.A. | Pad grid array and a method for producing such a pad grid array |
| US6566149B1 (en) * | 1998-09-16 | 2003-05-20 | Hitachi, Ltd. | Method for manufacturing substrate for inspecting semiconductor device |
| JP2002324819A (en) * | 2001-04-24 | 2002-11-08 | Matsushita Electric Works Ltd | Ic mounting board and method for manufacturing the same |
| JP4604387B2 (en) * | 2001-04-24 | 2011-01-05 | パナソニック電工株式会社 | IC mounting board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2570628B2 (en) | Semiconductor package and manufacturing method thereof | |
| KR100394809B1 (en) | Semiconductor package and method for manufacturing the same | |
| JP3414342B2 (en) | Mounting structure and mounting method of integrated circuit chip | |
| JP4023723B2 (en) | Surface mount type light emitting diode | |
| JP2001326236A (en) | Manufacturing method of semiconductor device | |
| US5844319A (en) | Microelectronic assembly with collar surrounding integrated circuit component on a substrate | |
| JPS63220533A (en) | Mounting structure of ic for clock | |
| JP3501281B2 (en) | Semiconductor device | |
| JP3307207B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH02163950A (en) | Mounting of semiconductor device | |
| US7589402B2 (en) | Semiconductor module and manufacturing method thereof | |
| JP3080049B2 (en) | Integrated circuit chip mounting structure and method | |
| JP3405136B2 (en) | Electronic component, method of manufacturing electronic component, and mounting structure of electronic component | |
| JP3006957B2 (en) | Semiconductor device package | |
| JPS61290799A (en) | Manufacture of electronic component | |
| JP2721790B2 (en) | Semiconductor device sealing method | |
| JPH06103701B2 (en) | Semiconductor device mounting body | |
| JP2505359Y2 (en) | Semiconductor mounting board | |
| JPH0225251Y2 (en) | ||
| JP2542227B2 (en) | Hybrid IC board device | |
| JPH11224886A (en) | Semiconductor device mounting structure | |
| KR0185961B1 (en) | Semiconductor package | |
| JPH04240741A (en) | Semiconductor device | |
| JPH0744199B2 (en) | Semiconductor device mounting body and mounting method thereof | |
| JPS6223119A (en) | Semiconductor device |