WO1999063589A1 - Pad grid array and a method for producing such a pad grid array - Google Patents

Pad grid array and a method for producing such a pad grid array Download PDF

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Publication number
WO1999063589A1
WO1999063589A1 PCT/EP1999/003801 EP9903801W WO9963589A1 WO 1999063589 A1 WO1999063589 A1 WO 1999063589A1 EP 9903801 W EP9903801 W EP 9903801W WO 9963589 A1 WO9963589 A1 WO 9963589A1
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WO
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Application
Patent type
Prior art keywords
ƒ
grid array
da
characterized
substrate
Prior art date
Application number
PCT/EP1999/003801
Other languages
German (de)
French (fr)
Inventor
Rolf Aschenbrenner
Joachim KLÖSER
Erik Jung
Luc Boone
Marcel Heerman
Jozef Van Puymbroeck
Original Assignee
Siemens S.A.
De Steur, Hubert
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0367Metallic bump or raised conductor not used as solder bump
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09045Locally raised area or protrusion of insulating substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09118Moulded substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/027Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha, beta particles

Abstract

According to the invention, an electrically insulating substrate (S1) is provided with a plurality of longitudinally extended, elevated waves (W1) on the underside thereof. The conductor pattern is applied on the underside of the substrate by means of laser structuring such that the terminal pads (P1) are arranged in a flat manner in the grid array, and each is situated in the crest area of a wave. The inventive pad grid array can be produced with a fine grid of, for example, 250 νm.

Description

description

Pad grid array and methods for producing such a pad grid arrays

Integrated circuits always get higher connection speeds and are always further miniaturized. The expected at this increasing miniaturization difficulties with solder paste and component sol len be resolved by new housing forms, especially single, Few- or multi-chip modules in a ball grid array package are emphasized (DE-Z produc- tronic 5, 1994, pages 54, 55). These modules are based on a contacted substrate on which the chips, for example, via contact or by means of flip-chip mounting are contacted. is at the bottom of the substrate the ball grid array (BGA), which is often referred to as Solder Grid Array or solder bump array. The ball grid array comprises on the bottom side of the substrate surface arranged bumps that allow surface mounting on the printed circuit boards or modules. The planar arrangement of the solder bumps high numbers of terminals can be realized, for example, 1.27 mm in a coarse grid.

In so-called. MID technology (MID = Molded Interconnection Devices) injection-molded parts are used with integrated conductor tracks instead of conventional printed circuits. High quality thermoplastics which are suitable for injection molding of three-dimensional substrates, are the basis of this technology. Such thermoplastics are distinguished over conventional substrate materials for printed circuits by better mechanical, chemical, electrical and environmental characteristics of egg. In one specific direction of MID technology, the so-called. SIL technique (SIL = Spitz molded parts with integrated conductive tracks), they are structuring a layer applied to the molded parts metal layer, dispensing with the usual mask technique using a special laser patterning method. a plurality of mechanical and electrical functions thereby be integrated into the three-dimensional injection-molded parts with of structured metallization. The housing support functions are performed at the same time guides and snap connections, while in addition to the wiring and connection function, the metallization layer also serves as an electromagnetic shield and provides a good heat dissipation. For the production of electrically conductive cross-connections between two wiring systems on opposite surfaces of the injection molded parts are already generated during the injection molding corresponding via holes. The inner walls of the via holes are then also coated in Metallsisieren of injection molded parts with a metal layer. Further details for the preparation of three-dimensional injection-molded parts with inte- grated circuit lines become apparent for example from DE-A-37 32 249 or EP-A-0361192.

From WO-A-89/10005 a die package is known, the existing of a plastic carrier body at the edge disposed on its underside with four and integrally angformten ribs is provided. The actual wiring here consists of a flexible circuit that is applied to the top or the bottom of the carrier body and wound around the peripheral rib, with corresponding external terminals are formed in the apex region of the ribs. The flexible wiring carrying one or more IC chips, which are then arranged according to Ausführunsform on the top or the bottom of the carrier body.

From WO-A-89/00346 a single-chip module is known in which the injection-molded, three-dimensional sub- strat of an electrically insulating polymer on the underside of the substrate during injection-molded bumps carries the optionally be arranged flat can. On the upper surface of this substrate, an IC chip is arranged, the terminals are connected via fine bonding wires formed on the top of the substrate traces. These conductive paths are in turn connected by vias with associated, formed on the protuberances external terminals.

is a so-called. Polymer stud grid array (PSGA) known from WO-A-96/096 46, which combines the advantages of ball grid arrays (BGA) with the advantages of MID technology. The name of the new design as a polymer stud grid array (PSGA) was carried out on the basis of the ball grid array (BGA), the term is intended to indicate the injection molding of the substrate-molded polymer studs "polymer stud". The new for single-, Few - or multi-chip modules includes appropriate design - an injection molded, three-dimensional substrate of an electrically insulating polymer, on the underside of the substrate surface arranged and during injection-molded polymer bumps on the polymer studs by a solderable Endober- surface formed external terminals, at least on the bottom of the substrate formed conductor tracks that connect the external connections to internal connections, and at least one disposed on the substrate chip whose connections are electrically conductively connected to the internal connections.

In addition to the simple and inexpensive production of the polymer studs during the injection molding of the substrate, the production of the external connections to the Polymerhök- can kern be made with minimal effort along with the usual in MID technology and SIL-technology manufacturing of the conductors. The preferred in the SIL technique fine laser structuring the external terminals can be realized on the polymer studs with high numbers of terminals in a fine grid. When derzeitgen state of the injection molding, however, a grid of 0.8 mm and a diameter of the polymer studs of 0.3mm must be regarded as a lower limit, since the injection mold in the region of the polymer studs can not be safely filled with plastic in a further miniaturization.

The dates indicated in claims 1 and 11, the invention is based on the problem to provide a new housing design having on the one hand the advantages of the polymer stud grid array (PSGA) and on the other hand, further miniaturization with a grid of the terminal pads of less than 0, 8 mm possible.

The invention is based on the finding that a substrate having elongated shafts in comparison to the

Substrate of a polymer stud grid array (PSGA) can be realized in a much finer geometry. Thus, during the injection molding of a substrate which correspond to the areas of the injection mold shafts can be much more easily filled with plastic, than the corresponding polymer bumps areas of an injection mold. Also of note is that the suitable for producing a wave-shaped substrate injection mold can be made much simpler and cheaper than the required for the preparation of a substrate of a polymer stud grid array injection mold. The formation of the conductor pattern with the terminal pads on the corrugated bottom of the substrate can be easily made in the required fineness by laser structuring. If the apex regions of the waves seen in the longitudinal direction of the shafts assigned to the connection pads of the conductor pattern, so pad grid arrays may be realized, for example, 250 microns with a fine grid.

Advantageous embodiments of the pad grid arrays according to the invention are given in claims 2 to 10 degrees.

Advantageous embodiments of the method according to the invention for producing a pad grid arrays are given in claims 11 to. 13

Of claim 2 relates to the transformation of the pad grid arrays to a solder grid array. Since the main- taining the required distance between the new package shape, and a printed circuit board is already ensured by the waves, the bumps have here the task alone, the connection pads with the associated terminals of the circuit board electrically conductive to be connected to. According to claim 3 of tin-lead alloys are particularly well suited for such solder joints.

The embodiment according to claim 4 facilitates formation of the solder bump by melting an electrolytically applied layer of solder, since the reduced in the conductor regions prevent drainage of the liquid solder on the circuit lines. The reduced width in the conductor regions can according to claims 5 and 6 in a simple manner by a constriction of the conductor tracks or are formed by introduced into the central region of the conductor tracks holes. The specified in claim 7. geometry of the connection pads and the reduced in the conductor regions enables an optimal formation of the solder bump by melting the electrolytically deposited solder layer. In preferred to claim 8 and adapted to a substrate provided with wave grid dimensions of the terminal pads are provided.

The further development according to claim 9 provides an additional Lotzufuhr in the formation of solder bumps by remelting electrolytically applied solder layers. Here, optimum conditions result when the specified in claim 10 of the corresponding geometry Lotzu- is maintained drove structures.

The embodiment of the method for manufacturing a pad grid array according to claim 12 allows an especially easy formation of solder bumps on the connection pads by remelting electrolytically applied solder layers. This remelting can thereby be rapidly and selectively according to claim 13 using a laser beam.

Embodiments of the invention are shown in the drawings and will be described in more detail below.

Show it

Figure 1 is a perspective view of an injection-molded and provided with shafts substrate, Figures 2 to 5 shows different stages of the procedure in the preparation of solder bumps provided with pad grid array on the substrate of Figure 1,

6 shows a first possibility for the realization of the connection pads and their connection with the secondary conductor lines,

7 shows a second possibility for the realization of the connection pads and their connection with the secondary conductor lines and Figure 8 is a comparison of the waveforms of a form suitable for flip chip pad grid arrays and a suitable surface mount pad grid arrays.

1 shows a perspective view of an electrically insulating substrate Sl, which is provided on its in the drawing upturned underside with a plurality of mutually parallel, raised waves Wl. The waves Wl are formed by integrally molded ribs of the substrate Sl produced by injection molding. As substrate materials of high-temperature-resistant thermoplastics, such as polyetherimide, polyethersulfone or Liquid Cri polymer are, for example stalline suitable.

On the underside of the substrate shown in Figure 1 a pad grid array is to be formed, the connection pads are located at the points marked with stars locations respectively in the apex region of the waves Wl. The indicated by the star pattern of the connection pads for example, can be realized in sizes between 250 microns and 500 microns.

In the preparation of a pad grid arrays, the substrate Sl shown in Figure 2 in cross section is first metallized over the entire surface by chemical deposition of copper, after which the desired conductor pattern including the connection pads produced by laser structuring on the underside of the substrate Sl. For this laser scribing, for example, an Nd: YAG laser with a wavelength of 1.06 microns used. Then, the electroless plated copper layer is enhanced to complete the conductor pattern by the electrolytic deposition of copper. The electrolytic deposition of metal on the conductor pattern is possible, for example, by the cathodic contacting of a manifold, not shown in the drawing, connecting all conductive areas of the conductor pattern with each other, and is later removed, for example by means of a laser beam. The apparent from FIG 3 conductive pattern comprises lying in the apex regions of the waves Wl connection pads Pl and which outgoing conductor tracks LZ, and other structures that result for example from the at later point still to be explained Figures 7 and 8. FIG.

According to Figure 4, a solder layer LO is then applied to the conductor pattern by electrodeposition. In the described embodiment is in the solder layer LO to a tin-lead alloy is deposited in a thickness of between 15 .mu.m and 50 .mu.m.

Subsequently, the electrolytically deposited solder is melted by heating to a temperature above the melting point temperature, whereby LH1 form by the surface tension of the liquid solder on the connection pads Pl is the apparent from Figure 5 of solder bumps themselves. In the described embodiment, the remelting is carried out by means of a indicated in Figure 5 by an arrow LST laser beam and selectively limited to the connection pads Pl and the reference to the figures 7 and 8 to be discussed later surrounding area. This laser remelting, the turbelastung only a minimal temperature in comparison with known remelting requires the substrate Sl, for example, is carried out again by means of a Nd: YAG laser with a wavelength of 1.06 microns.

Figure 6 shows a first possibility for the formation of the connection pads Pl and its vicinity. The geometry is shown as a developed view of the conductor pattern. The connection between the Connection pads Pl and the further conductor tracks LZ via necked conductor regions LB1 having a width between 10 microns and 40 microns and a length see be- Pl between I00xl00μm 2 und250x250μm 2 in dimensions of the connection pads 100 microns and 500 have microns. This constricted conductor regions LB1 prevent remelting of the ele- krolytisch applied solder layer LO (see FIG. 6) flowing away of the liquid solder on the circuit lines LZ. Moreover terbereichen on the managerial LB1 an additional solder volume for by the solder layer LO

Formation of the solder bumps LH1 (see FIG. 5) is provided. by chain-dotted lines in Figure 7 shown Lotzufuhrstrukturen LS leading away Pl of the individual connection pads, in a comparable manner, a further increase in the volume of the solder bumps LH1 (see FIG. 5) can be effected. Accordingly, these Lotzufuhrstrukturen LS as the conductor regions LB1 to have a width between 10 microns and 40 microns and a length of between 100 microns and 500 microns. In addition, a may in each case be the direction away from the individual connection pads Pl Lotzufuhrstrukturen LS connected to said earlier manifold which tallabscheidung in the electrolytic metal is contacted to the conductor pattern cathodically and is later separated from the rest of the conductive pattern. If the formation of the solder bumps LH1 by remelting of the solder layer LO with the aid of a laser beam LST (see FIGS. 4 and 5), the highly out of focus asked laser beam LST is each selectively via the connection pad Pl, the conductor portion LB1 and possibly via the Lotzufuhrstrukturen LS rasterized. Since the scanning can be performed in less than 0.1 seconds, the remelting takes place virtually simultaneously.

Figure 7 shows a second possibility for the formation of the indicated here with P10 connection pads and their immediate vicinity. Here, in the connecting region between the connecting pad P10 and a further LEI LZ terzug centrally a hole L is introduced. This gives rise to both sides of the hole L in the width of reduced conductor regions LB2. Additional Lotzufuhrstrukturen LS are again indicated by strichpunktier- te lines also in FIG. 8

The above-described pad grid arrays or after the application of solder bumps LH1 or LH2 (see FIGS. 5 or 6) Solder resulting grid arrays can be used for the flip chip and surface mount. However, the waves of the substrate must be of different heights formed. A comparison between suitable for flip chip waves W3 and the much higher suitable for surface mounting waves W4 shown in FIG 8. This is a theoretical juxtaposition, as must be in a pad grid array all terminal pads in one plane and therefore must be the same all the waves of a substrate always.

It is still pointed out that the waves formed on the underside of a substrate can also have other shapes than shown in the drawing and may extend to one another, for example, concentric. In addition, the shafts must be viewed in the longitudinal direction are not of constant height. Thus, the waves could seen in the longitudinal direction, for example each comprising between two connection pads indentations or notches. By this measure the elasticity of the connection pads is further increased on the waves, ie mechanical stresses caused by temperature fluctuations or the like. Can be better avoided.

Claims

Patentanspr├╝che
1. pad grid array, with an electrically insulating substrate (Sl; S2), - a plurality of elongated, raised shafts (WI; W3; W4) on the underside of the substrate (Sl; S2), and to the bottom of the substrate (Sl) applied conductor pattern, the Anschluß pads (Pl, P2; P10) of the conductor pattern are flächig arranged in the grid array, and in each case in the apex region of a shaft (WI; W3; W4) lie, and wherein - the waves (Wl) by integrally molded ribs of the substrate (Sl) are formed.
2. pad grid array according to claim 1, characterized in that the daß Anschluß pads (Pl, P10) Lothöcker (LHL) is applied.
3. pad grid array according to claim 2, characterized in that the Lothöcker (LHL) daß from a tin-lead alloy.
4. pad grid array according to any preceding Anspr├╝che, characterized in that the Anschlu├ƒ pads da├ƒ (Pl; P10) each ├╝ber a reduced width in the conductor region (LBL; LB2) with the weiterf├ ╝hrenden Leiterz├╝gen (LZ) are connected to the conductor pattern.
5. pad grid array according to claim 4, characterized in daß the reduced in the conductor regions (LBL) are formed by a Einschnürung the Leiterzüge (LZ).
6. pad grid array according to claim 4, characterized in that the daß reduced in the conductor regions (LBZ) introduced by into the central region of the Leiterzüge (LZ) Löcher (L) are formed.
7. pad grid array according to one of Ansprüche 4 to 6, characterized in that the daß Anschluß pads (Pl, P2; P10)? Fläche in their dimensions between 2 and 100xl00zw 250X250- M 2 have daß and the reduced in the conductor regions (LBL) has a width between 10 and 40 and a μm Länge between 100 and 500 comprise μm.
8. pad grid array according to any preceding Ansprüche, characterized in that the daß Anschluß pads (Pl, P2, P10) in a μm Rastermaß between 250 and 500 in the grid μm array are arranged.
9. Pad Grid Array according to one of Ansprüche 4 to 8, characterized in that daß by each Anschluß pads (Pl, P2; P10) in each case at least one, in the width of the width gegenüber the managerial terzüge (LZ) reduced Lotzufuhrstruktur (LS) wegführt.
10. Pad Grid Array according to any preceding Ansprüche, characterized in that the Lotzufuhrstrukturen (LS) daß a width between 10 and 40 and μm μm a Länge between 100 and 500 comprise μm ,
11. A method for producing a pad grid arrays comprising the steps of:
Preparing an electrically insulating substrate (Sl; S2), the underside of which a plurality of elongated, raised integrally formed shafts comprises depositing a metallization on the substrate (Sl; S2) (Wl, W4; W3),
Laser patterning of the metallization on the bottom of the substrate (Sl) sters to form a Leitermu- whose Anschluß pads (Pl; PIO) are arranged in the grid array, and in each case in the apex region of a shaft (W1 *; W3; W4) lying.
12. The method according to claim 11, characterized in that da├ƒ on the conductor pattern, a solder (LO) is applied electrolytically and da├ƒ the solder (LO) at least in the area of ​​Anschlu├ƒ pads (Pl; PIO) to form Loth├╢ckern (LHL; LH2) are remelted.
13. The method according to claim 12, characterized in that the solder (LO) daß using a laser beam (LST) is remelted.
PCT/EP1999/003801 1998-06-02 1999-06-01 Pad grid array and a method for producing such a pad grid array WO1999063589A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE19824636.6 1998-06-02
DE19824636 1998-06-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008112463A1 (en) * 2007-03-09 2008-09-18 Micron Technology, Inc. Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces

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Publication number Priority date Publication date Assignee Title
US3778532A (en) * 1972-07-03 1973-12-11 Illinois Tool Works Electrical circuit component having solder preform connection means
JPS63220533A (en) * 1987-03-10 1988-09-13 Citizen Watch Co Ltd Mounting structure of ic for clock
JPH01134885A (en) * 1987-11-20 1989-05-26 Furukawa Electric Co Ltd:The Surface packaging method for connector
US4926022A (en) * 1989-06-20 1990-05-15 Digital Equipment Corporation Laser reflow soldering process and bonded assembly formed thereby
WO1993002831A1 (en) * 1991-08-05 1993-02-18 Motorola, Inc. Solder plate reflow method for forming a solder bump on a circuit trace
US5288235A (en) * 1992-12-14 1994-02-22 Hughes Aircraft Company Electrical interconnects having a supported bulge configuration
WO1996009646A1 (en) * 1994-09-23 1996-03-28 Siemens N.V. Polymer stud grid array
US5612256A (en) * 1995-02-10 1997-03-18 Micron Display Technology, Inc. Multi-layer electrical interconnection structures and fabrication methods

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3778532A (en) * 1972-07-03 1973-12-11 Illinois Tool Works Electrical circuit component having solder preform connection means
JPS63220533A (en) * 1987-03-10 1988-09-13 Citizen Watch Co Ltd Mounting structure of ic for clock
JPH01134885A (en) * 1987-11-20 1989-05-26 Furukawa Electric Co Ltd:The Surface packaging method for connector
US4926022A (en) * 1989-06-20 1990-05-15 Digital Equipment Corporation Laser reflow soldering process and bonded assembly formed thereby
WO1993002831A1 (en) * 1991-08-05 1993-02-18 Motorola, Inc. Solder plate reflow method for forming a solder bump on a circuit trace
US5288235A (en) * 1992-12-14 1994-02-22 Hughes Aircraft Company Electrical interconnects having a supported bulge configuration
WO1996009646A1 (en) * 1994-09-23 1996-03-28 Siemens N.V. Polymer stud grid array
US5612256A (en) * 1995-02-10 1997-03-18 Micron Display Technology, Inc. Multi-layer electrical interconnection structures and fabrication methods

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PATENT ABSTRACTS OF JAPAN vol. 013, no. 386 (E - 812) 25 August 1989 (1989-08-25) *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008112463A1 (en) * 2007-03-09 2008-09-18 Micron Technology, Inc. Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces
US7928582B2 (en) 2007-03-09 2011-04-19 Micron Technology, Inc. Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces
US8492198B2 (en) 2007-03-09 2013-07-23 Micron Technology, Inc. Microelectronic workpieces with stand-off projections and methods for manufacturing microelectronic devices using such workpieces
US8987874B2 (en) 2007-03-09 2015-03-24 Micron Technology, Inc. Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces

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