JPS6321353B2 - - Google Patents

Description

Detailed Description of the Invention The present invention provides a V group compound semiconductor heterostructure MOSFET with high operating speed and low threshold voltage.
It provides:

A conventional MOSFET is configured as shown in FIG. In FIG. 1, 1 is a source, 2 is a drain, 3 is a semiconductor crystal, 4 is an oxide film, 5 is a gate, and 6 is a channel.

Although this normally-off inversion type FET is extremely useful for integration, it has the following problems. That is, in this inversion type FET, the surface portion of the semiconductor 3 located directly below the gate 5 is inverted by a gate voltage to form a channel 6 to allow a carrier to flow from the source 1 to the drain 2. At this time, the channel 6 is formed near the interface with the oxide film 4 on the crystal surface, so the crystal quality is not perfect, and the mobility of the carrier flowing there is lower than that deep inside the crystal. The drawback was that it interfered with the high-speed operation of the FET. On the other hand, stabilizing the crystal surface and creating a high-quality gate oxide film is necessary for MOSFETs.
However, at present, it cannot be obtained from any crystalline material. Therefore, even if an attempt is made to use a crystalline material with high mobility in order to increase the operating speed, it is unlikely that the material will have good surface characteristics, so silicon has traditionally been the only material used for MOSFETs. There was a problem that In addition, in order to reduce the gate voltage, that is, the threshold voltage, required for channel formation, it is desirable that the forbidden band width of the crystal material be small, but for the reasons mentioned above, there is a problem that there is no arbitrary selectivity. Ta.

In order to solve the problems of the conventional example described above, the present invention provides a group V compound heterostructure MOSFET in which the semiconductor layer in contact with the gate oxide film and the semiconductor layer in which the channel is formed are separated, and the semiconductor layer is separated from the semiconductor layer in contact with the gate oxide film and the semiconductor layer in which the channel is formed. It is characterized by the use of a -V group compound semiconductor with excellent heterojunctions. Hereinafter, embodiments will be described in detail with reference to the drawings.

FIG. 2 shows an embodiment of the present invention.
is the first layer substrate, 8 is the second layer, 9 is the third layer, 10
1 is a source, 11 is a drain, 12 is a gate oxide film, 13 is a gate electrode, and 14 and 15 are ohmic electrodes.

Next, a manufacturing method of this example will be described. First, a three-layer crystal substrate as shown in FIG. 3 is formed by epitaxial growth. The substrate 7 is p-type InP, the impurity concentration is arbitrary, and the second layer 8 is p-type In _1-x Ga _x As _y P _1-y
(0<x<1, 0<y≦1, and in this example, x
= 0.47, y = 1), and the impurity concentration is
The third layer 9 is p ^{-type InP and has an impurity concentration of 10 16 /} cm ^{3 .} This second layer 8 is made to match the InP of the first layer 7 and third layer 9 as much as possible, and the forbidden band width Eg ₂ of the second layer 8 is made smaller than the forbidden band width Eg ₁ of the first and third layers 7 and 9. reduce the range to Eg ₁ −Eg ₂ ＞
Set to 0.2eV. This energy difference Eg ₁ −Eg ₂ is
Calculations have revealed that when the voltage is 0.2 eV or less, electrons induced by the gate voltage are distributed and appear simultaneously on both the surface of the surface semiconductor layer 9 and the semiconductor layer 8, which is the purpose of the present invention. The effect of separating the semiconductor layer in contact with the gate oxide film and the semiconductor layer in which the channel is formed will be lost.
Further, the thickness of the third layer 9 is set to 0.1 μm, but there is no particular restriction on the first and second layers 7 and 8. The energy band of this three-layer crystal substrate is shown in FIG. 3b, and since each crystal layer 7 to 9 are both p-type,
The energy distribution of the conduction band becomes smaller in the second layer 8', and the second layer 8' is depressed compared to the first and third layers 7' and 9'. In addition, as shown in FIG. 2, the source 10 and drain 12 are made by type conversion by diffusion of n-type impurities, and the diffusion front reaches the second layer 8 or invades the first layer 7. That's what I do. Further, in the production of the gate portion, first, Al ₂ O ₃ is formed on the surface of the third layer 9 by the CVD method to form the gate oxide film 12, and the gate electrode 13 is formed of Al.

Next, FIG. 4 shows the energy band of the gate part during operation of this embodiment and shows how a channel is formed. FIG. 4a shows that the gate voltage is V _G = This is when the value is 0. In Figure 4,
E _i (dashed line) is the level of the center of the forbidden zone, E _F (dashed line)
is the Fermi level, and the reason why the energy on the semiconductor side is tilted when V _G =0 is because there is a difference in the work function of the Al electrode 11 and the surface semiconductor layer 9.
Generally, when E _i > _EF , it is p-type, and when E _i < _EF ,
Since it is n-type, when V _G =0, the entire semiconductor side is p-type and there is no inversion layer. However, ｜V _G ｜＞｜V _T
| (V _T is the gate voltage at which an inversion layer (channel) appears, and it was as low as 0.8 V.) In the second layer 8, E _i < _EF , and elsewhere E _i >E _F , so , it can be seen that an n-channel that causes electron conduction is formed in the second layer 8. That is, in Figure 2
This is because the source 10 and drain 11 of the MOSFET are electrically connected through the n-channel generated in the second layer 8.

Comparing this embodiment with the conventional MOSFET shown in FIG. 1, the above-mentioned problem of reduced mobility at the crystal surface is eliminated, and the switching speed is more than doubled in this embodiment. Also used for the second layer 8
Since the electron traveling speed of InGaAsP can be higher than that of InP, the operating speed can be increased. Furthermore,
As can be seen from FIG. 4, since a channel is formed in the second layer before the third layer 9 is inverted, the threshold voltage V _T can be lowered.

Note that the present invention can be effectively used in high-frequency MOSFETs, high-speed logic elements, high-speed shift registers, and the like.

As explained above, according to the present invention, since the surface crystal is not used as a channel but the internal layer is used as a channel, there is no decrease in mobility, high-speed operation can be performed, and currently stable operation is possible. Even if the interface characteristics are not obtained, as long as the mobility is high, it can be used as a channel, so high-speed operation is possible, and the threshold voltage V _T can be lowered, among other advantages.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the configuration of a conventional MOSFET, Figure 2 is a diagram showing the configuration of an embodiment of the present invention, Figure 3 is a diagram showing the crystal substrate energy band used in the present invention, and Figure 4 is a diagram showing the configuration of a conventional MOSFET. FIG. 2 is a diagram showing energy bands during operation of an embodiment of the present invention. 7...Substrate, 8,9...Crystal layer, 10...Source, 1
DESCRIPTION OF SYMBOLS 1...Drain, 12...Gate oxide film, 13...Gate electrode, 14, 15...Ohmic electrode.

Claims (1)

[Claims] 1 A p-type (or n-type)-V group compound semiconductor having a smaller band gap than the first crystal (energy gap E _g1 ) is formed on the first crystal (energy gap E g1 ) made of a p-type (or n-type)-V group compound semiconductor. A second crystal consisting of a semiconductor (E _g1
-E _g2 0.2eV; however, E _g2 is the energy forbidden band width of the second crystal), and a third crystal having the same composition as the first crystal is epitaxially grown on this second crystal in order. On a crystal substrate consisting of layers, n from the third crystal surface reaches the second crystal layer.
A drain and a source region of a type (or p-type) semiconductor are provided, and a gate portion made of an oxide film and metal is provided on a third crystal surface between the drain and source regions to form a second crystal with a small forbidden band width. A group V compound semiconductor heterostructure MOSFET characterized by having layers act as channels.