JPS599971A - Insulated gate field effect transistor - Google Patents
Insulated gate field effect transistorInfo
- Publication number
- JPS599971A JPS599971A JP11945282A JP11945282A JPS599971A JP S599971 A JPS599971 A JP S599971A JP 11945282 A JP11945282 A JP 11945282A JP 11945282 A JP11945282 A JP 11945282A JP S599971 A JPS599971 A JP S599971A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- type
- field effect
- effect transistor
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 13
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 7
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 claims description 3
- 238000007598 dipping method Methods 0.000 claims 1
- 229910017401 Au—Ge Inorganic materials 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 4
- 101000633752 Bitis arietans Snaclec 6 Proteins 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、絶縁ゲート電界効果トランジスタに関するも
のであり、特にモジュレーション・ドーピングされた砒
化ガリウムとガリウム・アルミ砒素の同形へテロ接合を
導電チャネルとして用いる絶縁ゲート電界効果トランジ
スタ（以下ＭＩＳＦＥＴとよぶ）を提供するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to insulated gate field effect transistors, and more particularly to insulated gate field effect transistors using modulation-doped gallium arsenide and gallium aluminum arsenide isomorphic heterojunctions as conducting channels. (hereinafter referred to as MISFET).
モジュレーション・ドーピングされたヘテロ接合は良く
知られているように、低温における電子移動度が極めて
大きい。この特長をいかして、従来、ｎ形ガリウム・ア
ルミ・砒素（以下、ｎ形ＧａｘＡｚ、、 Ａｓ と記
す）表面に金属ンヨノトキー電極を形成し、このショッ
トキー電極に印加する電圧によってｎ形砒素ガリウム層
（以下、ｎ形ＧａＡｓ と記す）に誘起される電子の
数を制御し、電界効果トランジスタとして動作させるも
のが考えられている。このショットキーゲートの電界効
果トランジスタの移動度は７７”Ｋにおいて、１ｏ５ｃ
ｒｌ／Ｖ−８程度と極めて高く、超高周波デバイスとし
て有用である。しかし、ゲート部がショノ１〜キー接合
であるため、正の電圧が印加できないということや、ゲ
ート部とソース電（ｊとを隔離せねばならないというこ
とのために、ソース抵抗が増大し、高周波化のさまたげ
になる等の欠点を有している。As is well known, modulation-doped heterojunctions have extremely high electron mobility at low temperatures. Taking advantage of this feature, conventionally, a metal Schottky electrode is formed on the surface of n-type gallium aluminum arsenic (hereinafter referred to as n-type GaxAz, As), and a voltage applied to this Schottky electrode is used to form an n-type gallium arsenide layer. It has been considered to control the number of electrons induced in GaAs (hereinafter referred to as n-type GaAs) and operate it as a field effect transistor. The mobility of this Schottky gate field effect transistor is 1o5c at 77"K.
It has an extremely high rl/V-8 or so, and is useful as an ultra-high frequency device. However, since the gate part is a one-key junction, a positive voltage cannot be applied, and the gate part and the source voltage (j) must be isolated, which increases the source resistance and causes high frequency It has disadvantages such as hindering the development of
本発明はこれもの従来の欠点を解決することを目的とす
るものであって、絶縁ゲートと自己整合ソース・ドレイ
ン電極を持った超高周波用の絶縁ケート電界効果トラン
ジスタを提供するものである。The present invention aims to overcome these conventional drawbacks and provides an insulated gate field effect transistor for very high frequencies having an insulated gate and self-aligned source and drain electrodes.
以下、本発明の絶縁ゲート電界効果トランジスタの詳細
に関し実施例を用いて説明する。Hereinafter, details of the insulated gate field effect transistor of the present invention will be explained using examples.
図に本発明の一実施例における絶縁ケート電界効果トラ
ンジスタの断面図を示す。まずｎ形で（１００）而を有
するＧａＡｓ 基板１１を用いる。The figure shows a cross-sectional view of an insulated gate field effect transistor according to an embodiment of the present invention. First, an n-type GaAs substrate 11 having a (100) structure is used.
このｎ形ＧａＡｓ 基板１１の不純物濃度は低くなけれ
ばならない。The impurity concentration of this n-type GaAs substrate 11 must be low.
本実施例では、不純物濃度が１０１５ＣＴＬ−６以下の
基板を用いた。次に分子線エピタキシャル法を用いてｎ
形Ａ４ Ｇａ１． Ａｓ ）ｆＪ １２を厚さ１００Ａ
程度のＨｌみに成長させる。ここで、不純物としてＳｎ
を用い、濃度は１〜３×１０ ＣＩｒＬ であった。In this example, a substrate with an impurity concentration of 1015 CTL-6 or less was used. Next, using the molecular beam epitaxial method, n
Shape A4 Ga1. As ) fJ 12 with thickness 100A
Grow to about HL size. Here, Sn as an impurity
was used, and the concentration was 1-3 x 10 CIrL.
この様にして票備しだウェハ上に、通常の化学気什成１
ｑ法（ｃｖｎ法）を用いてフィールド酸化膜数に電界効
果トランジスタ製作領域の５ｉｏ２膜１３を除去し、フ
ィールド酸化膜形成と同様にケート酸化膜１４を５００
人形成する。この後、グー１−金属１６としてモリブデ
ンを３０００ Ａ蒸着ｆ ル。In this way, a normal chemical atmosphere is formed on the wafer prepared.
Using the q method (cvn method), remove the 5io2 film 13 in the field effect transistor fabrication area to reduce the number of field oxide films, and remove the gate oxide film 14 in the same way as in the field oxide film formation.
Form people. After this, molybdenum was vapor-deposited at 3000 A as the metal 16.
次に、ゲート部分をフォト・レジストでマスクし、反応
性イオンエツチングによりゲート部を残してＭｏ と
ゲート酸化膜１４をエツチング除去する。Next, the gate portion is masked with a photoresist, and the Mo 2 and gate oxide film 14 are etched away, leaving the gate portion, by reactive ion etching.
次に、Ｓｉ イオンを注入（加速電圧−１６０Ｋｌ。Next, Si ions were implanted (acceleration voltage -160Kl).
１’−ス−ｊｊ（＝Ｉ Ｘｌ ０” ） ｊ、、グー７
スマＯＶ Ｄ 法ｆ用いて、窒化硅素膜Ｓｉ３Ｎ４１
７を５０００人蒸着し、７６０’Ｃ，２０分間熱処理を
施し、注入しだＳｉ 原子の活性化を計る。このよう
にして、高濃度（ＮＤ＝１ ｏ１８ｃｍ ’ ） ｎ
影領域１６を形成する。1'-su-jj (=I Xl 0'') j,, goo 7
Silicon nitride film Si3N41 using SmaOVD method
7 was deposited by 5000 people and heat treated at 760'C for 20 minutes to activate the implanted Si atoms. In this way, high concentration (ND=1 o18cm') n
A shadow area 16 is formed.
最後にｎ影領域１θにコンタクト窓をあけオーミック電
極１８をＡｕ −Ｇｅ合金を用いて形成する。Finally, a contact window is opened in the n-shaded region 1θ and an ohmic electrode 18 is formed using an Au-Ge alloy.
以上のようにして作製して得られた電界効果トランジス
タは、ｎ影領域１６をソース及びドレインとするエンハ
ンスメント形のＭＩＳＦＥＴである。ゲート電極１５直
下のＡノｘＧａ１． Ａｓ 層１２は常に空乏化してお
りソース・ドレイン間を流れる電流には寄与しない。ソ
ース・ドレイン間電流は、ＧａＡｓ ４％板１１とｎ形
ＡノＸＧａ１． Ａｓ層１．２のへテロ接合界面で、Ｇ
ａＡｓ基板１１側に誘起される電子によって流れる。す
なわち、ｎ形ＡノｘＧａ１．ン１輌１２は電子をｎ形Ｇ
ａ Ａｓ 爪板１１に供給する働きをし、この電子が
不純物濃度の低いｎ形ＧａＡｓ基板１１を流れる。した
がって、このＭＩＳＦＥＴを低温で動作させると、不純
物散乱がないので移動度は（”枳めて大きくなり、超高
周波動作が可能である。The field effect transistor manufactured as described above is an enhancement type MISFET in which the n-shaded region 16 serves as a source and a drain. AnoxGa1. directly below the gate electrode 15. The As layer 12 is always depleted and does not contribute to the current flowing between the source and drain. The source-drain current is between the GaAs 4% plate 11 and the n-type A-XGa1. At the heterojunction interface of As layer 1.2, G
The flow is caused by electrons induced on the aAs substrate 11 side. That is, n-type AnoxGa1. 1 car 12 converts electrons into n-type G
a As serves to supply the nail plate 11, and these electrons flow through the n-type GaAs substrate 11 with a low impurity concentration. Therefore, when this MISFET is operated at a low temperature, the mobility is significantly increased because there is no impurity scattering, and ultra-high frequency operation is possible.
また、ｎ形Ａｊ！−ｘＧａｌ−ｘ ＡＳ 層１２の厚さ
を厚く（＝１０００人）すればデプレッション形動作の
ＭＩＳＦＥＴを実現できる、。Also, n-type Aj! -xGal-x AS If the thickness of the layer 12 is increased (=1000 layers), a MISFET with depression mode operation can be realized.
以］−に述べたように本発明の絶縁ゲート電界効果トラ
ンジスタを用いると、ゲートの入力インピータンスが高
く、かつソース・ゲート抵抗が極めて小さなＦＥＴを実
現することができる。しだがって、従来になく高速動作
が可能であるのみならず、集積化という点でも優れた効
果を発揮する。As described above, by using the insulated gate field effect transistor of the present invention, it is possible to realize an FET with high gate input impedance and extremely low source-gate resistance. Therefore, not only is it possible to operate at a higher speed than ever before, but it also exhibits excellent effects in terms of integration.
図は本発明の実施例における絶縁ゲート電界効果トラン
ジスタの断面図を示す。
１１・・・・・・ｎ形低濃度ＧａＡｓ 基板、１２・・
・・・ｎ７１９ｊ 高濃度Ａ４ Ｇａ１． Ａｓ エ
ピタキシャル層、１３・・・・・フィールド酸化膜層、
１４・・・・・ゲート酸化膜層、１５・・・・・・ゲー
ト金属、１６・・・・・高濃度ｎ形拡散層、１７・・・
・・・層間絶縁膜、１８・・・・・・オーミック電極。The figure shows a cross-sectional view of an insulated gate field effect transistor in an embodiment of the invention. 11...N-type low concentration GaAs substrate, 12...
...n719j High concentration A4 Ga1. As epitaxial layer, 13... field oxide film layer,
14...Gate oxide film layer, 15...Gate metal, 16...High concentration n-type diffusion layer, 17...
...Interlayer insulating film, 18...Ohmic electrode.
Claims (1)
アルミー砒素のエピタキシャル層が形成され、前記ｎ形
高濃度ガリウム・アルミ・砒素層の上に、開孔部を有す
る第１の絶縁膜が形成され、前記開孔部の前記ガリウム
・アルミ・砒素層の上に金属膜が漬１・Δされた第２の
絶縁膜が形成されることによって前記開孔部が２つに分
割され、この分割された開化部を通して不純物が導入さ
れた前記基板に達する深さの高濃度ｎ影領域が形成され
、１）１■記金属膜をゲート電極、０１１記２つの高濃
度ｎ影領域をソース・ドレインとすることを特徴とする
絶縁グー１〜電界効果トランジスタ。N-type high concentration gallium arsenide on n-type low concentration gallium arsenide substrate
An epitaxial layer of aluminum arsenic is formed, a first insulating film having an opening is formed on the n-type high concentration gallium-aluminum-arsenic layer, and the gallium-aluminum-arsenic layer is located in the opening. By forming a second insulating film on which a metal film is dipping 1·Δ, the opening is divided into two parts, and the impurity is introduced into the substrate through the divided opening. Insulating goo 1 to field effect transistor characterized in that a deep high concentration n shadow region is formed, 1) the metal film 1) is used as a gate electrode, and the two high concentration n shadow regions 011 are used as a source/drain .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11945282A JPS599971A (en) | 1982-07-08 | 1982-07-08 | Insulated gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11945282A JPS599971A (en) | 1982-07-08 | 1982-07-08 | Insulated gate field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS599971A true JPS599971A (en) | 1984-01-19 |
Family
ID=14761729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11945282A Pending JPS599971A (en) | 1982-07-08 | 1982-07-08 | Insulated gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS599971A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5220194A (en) * | 1989-11-27 | 1993-06-15 | Motorola, Inc. | Tunable capacitor with RF-DC isolation |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55117281A (en) * | 1979-03-05 | 1980-09-09 | Nippon Telegr & Teleph Corp <Ntt> | 3[5 group compound semiconductor hetero structure mosfet |
| JPS56104472A (en) * | 1980-01-24 | 1981-08-20 | Sumitomo Electric Ind Ltd | Semiconductor device |
-
1982
- 1982-07-08 JP JP11945282A patent/JPS599971A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55117281A (en) * | 1979-03-05 | 1980-09-09 | Nippon Telegr & Teleph Corp <Ntt> | 3[5 group compound semiconductor hetero structure mosfet |
| JPS56104472A (en) * | 1980-01-24 | 1981-08-20 | Sumitomo Electric Ind Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5220194A (en) * | 1989-11-27 | 1993-06-15 | Motorola, Inc. | Tunable capacitor with RF-DC isolation |
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