JPS6320858A - Manufacture of package for housing semiconductor element - Google Patents
Manufacture of package for housing semiconductor elementInfo
- Publication number
- JPS6320858A JPS6320858A JP61166464A JP16646486A JPS6320858A JP S6320858 A JPS6320858 A JP S6320858A JP 61166464 A JP61166464 A JP 61166464A JP 16646486 A JP16646486 A JP 16646486A JP S6320858 A JPS6320858 A JP S6320858A
- Authority
- JP
- Japan
- Prior art keywords
- external lead
- lead frame
- external
- metal layer
- brazing material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000463 material Substances 0.000 claims abstract description 34
- 238000005219 brazing Methods 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 12
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 8
- 239000000919 ceramic Substances 0.000 description 6
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 238000005476 soldering Methods 0.000 description 5
- 238000004080 punching Methods 0.000 description 4
- 239000011572 manganese Substances 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- NEIHULKJZQTQKJ-UHFFFAOYSA-N [Cu].[Ag] Chemical compound [Cu].[Ag] NEIHULKJZQTQKJ-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910000833 kovar Inorganic materials 0.000 description 2
- 229910052748 manganese Inorganic materials 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910017709 Ni Co Inorganic materials 0.000 description 1
- 229910003267 Ni-Co Inorganic materials 0.000 description 1
- 229910003262 Ni‐Co Inorganic materials 0.000 description 1
- 229910000978 Pb alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003463 adsorbent Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子を収納するための半導体素子収納用
パフケージの製造法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a puff cage for housing semiconductor elements.
従来、半導体素子、特に半導体集積回路素子を収納する
ための半導体素子収納用パンケージは、第４図に示すよ
うにアルミナセラミックス等の電気絶縁材料から成り、
その上面周縁部にモリブデン（Ｍｏ） 、マンガン（Ｍ
ｎ）、タングステン（匈）等の高融点金属粉末から成る
多数個の金属層１２を有する方形状の絶縁基体１１と、
半導体素子を外部回路に電気的に接続するために前記金
属層１２にロウ付けされた外部リード端子１３と蓋体１
４とから構成されており、絶縁基体１１と蓋体１４とか
ら成る絶縁容器内部に半導体素子１５が収納され、気密
封止されて半導体装置となる。Conventionally, semiconductor element housing pancases for housing semiconductor elements, particularly semiconductor integrated circuit elements, have been made of electrically insulating materials such as alumina ceramics, as shown in FIG.
Molybdenum (Mo) and manganese (M
n) a rectangular insulating substrate 11 having a large number of metal layers 12 made of high melting point metal powder such as tungsten;
External lead terminals 13 and lid 1 brazed to the metal layer 12 to electrically connect the semiconductor element to an external circuit.
A semiconductor element 15 is housed inside an insulating container consisting of an insulating base 11 and a lid 14, and is hermetically sealed to form a semiconductor device.
かかる従来の半導体素子収納用パッケージは通常、以下
に述べる方法によって製作される。Such conventional packages for housing semiconductor elements are usually manufactured by the method described below.
即ち、第５図に示すように、まず、表面に金属ペースト
を印刷塗布した複数枚の未焼成セラミツクシートを積層
し、これを還元雰囲気中で焼成して金属層１２を有する
絶縁基体１１を得るとともに複数の外部リード端子１３
を有するリードフレーム１６を４！備し、次に、前記絶
縁基体１１上に方形環状のロウ材１７を介してリードフ
レーム１６を載置するとともに各金属層１２とこれに対
応する各外部リード端子１３とを位置合わせし、しかる
後、これを約９００℃の温度に加熱し、ロウ材１７を溶
融させて金属層１２と外部リード端子１３とをロウ付は
固着するとともに外部リード端子１３をリードフレーム
１６より切断分離することによって製作される。That is, as shown in FIG. 5, first, a plurality of unfired ceramic sheets whose surfaces are printed and coated with a metal paste are laminated and then fired in a reducing atmosphere to obtain an insulating substrate 11 having a metal layer 12. together with a plurality of external lead terminals 13
Lead frame 16 with 4! Next, the lead frame 16 is placed on the insulating substrate 11 via the rectangular annular brazing material 17, and each metal layer 12 and each corresponding external lead terminal 13 are aligned. Thereafter, this is heated to a temperature of about 900° C. to melt the brazing material 17 and braze the metal layer 12 and the external lead terminal 13, and at the same time cut and separate the external lead terminal 13 from the lead frame 16. Manufactured.
しかし乍ら、この従来の半導体素子収納用パッケージの
製造法によれば、絶縁基体１１に設けられた各金属層１
２と各外部リード端子１３とをロウ付は固着させるロウ
材１７が、そのロウ付けの作業性を良好とするために方
形環状を成しており、そのため該方形環状のロウ材１７
を加熱溶融させ各金属層１２に外部リード端子１３をロ
ウ付は固着する際、ロウ材１７の各隅部のものがリード
フレーム１６の各辺に設けた外部リード端子１３のうち
各辺両端に位置するものに溶融付着し、その結果、リー
ドフレーム１６の各辺両端に位置する外部リード端子１
３はそのロウ付けのロウ材量が過多となり、ロウ付は強
度が大きく低下するという欠点を有していた。However, according to this conventional manufacturing method of a package for storing semiconductor elements, each metal layer 1 provided on the insulating base 11
2 and each external lead terminal 13 is formed into a rectangular ring shape in order to improve the workability of brazing.
When soldering or fixing the external lead terminals 13 to each metal layer 12 by heating and melting the solder material 12, the solder material 17 at each corner is attached to both ends of each side of the external lead terminals 13 provided on each side of the lead frame 16. As a result, the external lead terminals 1 located at both ends of each side of the lead frame 16
No. 3 had the disadvantage that the amount of brazing material used in the brazing was excessive, and the strength of the brazing was greatly reduced.
本発明は上記欠点に鑑み案出されたもので、その目的は
絶縁容器に設けた金属層に所定の外部リード端子を強固
にロウ付は固着することができる半導体素子収納用パッ
ケージを提供することにある。The present invention has been devised in view of the above-mentioned drawbacks, and its purpose is to provide a package for housing semiconductor elements in which predetermined external lead terminals can be firmly soldered or fixed to a metal layer provided in an insulating container. It is in.
本発明の半導体素子収納用パッケージの製造法は、
内部に半導体装置を収納するための空所を有し、かつ上
面もしくは下面の周縁部に複数個の金属層が被着形成さ
れた方形状の絶縁容器を準備し、複数個の外部リード端
子及びダミーリードを備えたリードフレームを方形環状
のロウ材を介して前記絶縁容器上に載置し、各外部リー
ド端子をこれに対応する各金属層に、またダミーリード
を方形状環状のロウ材の各隅部に位置合わせし、次いで
、前記ロウ材を加熱溶融させ、各外部リード端子をそれ
に対応する各金属層上に固着し、その後、前記各外部リ
ード端子をリードフレームより切断し、該リードフレー
ムを除去することを特徴とするものである。The method for manufacturing a package for accommodating a semiconductor element of the present invention includes a rectangular package having a cavity for accommodating a semiconductor device therein and having a plurality of metal layers adhered to the periphery of the upper or lower surface. An insulating container is prepared, a lead frame equipped with a plurality of external lead terminals and dummy leads is placed on the insulating container via a rectangular ring-shaped brazing material, and each external lead terminal is connected to each metal layer corresponding to the lead frame. In addition, the dummy leads are aligned with each corner of the rectangular annular brazing material, and then the brazing material is heated and melted to fix each external lead terminal onto the corresponding metal layer. This method is characterized in that each external lead terminal is cut from the lead frame and the lead frame is removed.
次に本発明を第１図乃至第３図に示す実施例に基づき詳
細に説明する。Next, the present invention will be explained in detail based on the embodiment shown in FIGS. 1 to 3.
本発明の半導体素子収納用パッケージの製造に当たり、
まず第１図に示すような半導体素子を収納するだめの絶
縁容器を構成する絶縁基体ｌが準備される。In manufacturing the semiconductor element storage package of the present invention,
First, an insulating substrate l constituting an insulating container for accommodating a semiconductor element as shown in FIG. 1 is prepared.
前記絶縁基体１はその上面中央部に半導体素子を収納す
るための凹部Ａが形成されており、該凹部Ａ内には半導
体素子（不図示）が取着固定される。A recess A for accommodating a semiconductor element is formed in the center of the upper surface of the insulating base 1, and a semiconductor element (not shown) is fixedly attached within the recess A.
また前記絶縁基体１の凹部周辺から上面周縁部にかけて
複数個の金属層−２が形成されており、該金属層２の凹
部周辺部には内部に収納する半導体素子の各電極が金属
細線（ボンディングワイヤ）を介し接続される。Further, a plurality of metal layers 2 are formed from the periphery of the recess to the periphery of the upper surface of the insulating substrate 1, and each electrode of the semiconductor element to be housed inside is formed around the recess of the metal layer 2 by thin metal wires (bonding). wire).
前記絶縁基体ｌ及び金属層２は表面に金属ペーストを印
刷塗布した未焼成セラミツクシート（グリーンシート）
を複数、枚積層するとともに還元雲囲気中（ＩＩ ｚ
−Ｎ ｔガス中）、約１４００〜１６００℃の高温で焼
成することによって形成される。The insulating base 1 and the metal layer 2 are unfired ceramic sheets (green sheets) whose surfaces are coated with a metal paste.
In addition to stacking multiple layers of
-Nt gas) at a high temperature of about 1400-1600°C.
尚、前記未焼成セラミツクシートはアルミナ（八１ｔ（
ｈ） 、シリカ（ＳｉＯ□）等のセラミック原料粉末に
適当な溶剤、溶媒を添加混合して泥漿物を作り、これを
従来周知のドクターブレード法によりシート状と成すこ
とによって形成される。The unfired ceramic sheet is made of alumina (81t).
h) It is formed by adding and mixing a suitable solvent to a ceramic raw material powder such as silica (SiO□) to form a slurry, and forming the slurry into a sheet by a conventionally well-known doctor blade method.
また金属ペーストはタングステン（−）、モリブデン（
Ｍｏ）、マンガン（Ｍｎ）等の高融点金属粉末に適当な
溶剤、溶媒を添加混合することによって作成され、未焼
成セラミツクシート表面に従来周知のスクリーン印刷等
の厚膜手法によって印刷塗布される。In addition, metal pastes include tungsten (-) and molybdenum (
It is prepared by adding and mixing a suitable solvent to a high melting point metal powder such as Mo) or manganese (Mn), and is printed and coated on the surface of an unfired ceramic sheet by a conventionally well-known thick film method such as screen printing.
次に、第１図に示すような四辺のそれぞれに複数個の外
部リード端子３を有する方形状のリードフレーム４およ
び方形環状のロウ材５が準備される。Next, a rectangular lead frame 4 having a plurality of external lead terminals 3 on each of its four sides and a rectangular annular brazing material 5 as shown in FIG. 1 are prepared.
前記外部リード端子３およびリードフレーム４はコバー
ル（Ｆｅ−Ｎｉ−Ｃｏ合金）や４２Ａ１１ｏｙ（Ｆｅ−
Ｎｉ合金）等の金属から成り、該外部リード端子３は内
部に収納する半導体素子の各電極を外部回路に電気的に
接続する作用を為す。The external lead terminal 3 and lead frame 4 are made of Kovar (Fe-Ni-Co alloy) or 42A11oy (Fe-
The external lead terminal 3 serves to electrically connect each electrode of the semiconductor element housed inside to an external circuit.
前記複数個の外部リード端子３を有するリードフレーム
４は各外部リード端子３の位置をリードフレーム４によ
って規制しており、各外部リード端子３のそれぞれは絶
縁基体１の上面に設けた金属ｊ！ｉ２の周縁部に銀ロウ
等の接着材を介し取着される。The lead frame 4 having the plurality of external lead terminals 3 regulates the position of each external lead terminal 3, and each external lead terminal 3 is connected to a metal j! provided on the upper surface of the insulating base 1. It is attached to the peripheral edge of i2 via an adhesive such as silver solder.
また、前記リードフレーム４にはその四隅にダミーリー
ド６が設けてあり、該ダミーリード６はその先端を後述
する方形環状を成すロウ材５の各隅部Ｂ上に載置するこ
とによって外部リード端子３を金属層２にロウ付は固着
するためにロウ材５を加熱溶融させた際、ロウ材５の隅
部Ｂのものが外部リード端子３に過多に溶融付着しない
よう吸着する作用を為す。 。Further, the lead frame 4 is provided with dummy leads 6 at its four corners, and the tips of the dummy leads 6 are placed on each corner B of a brazing material 5 forming a rectangular ring shape, which will be described later. When the soldering material 5 is heated and melted in order to fix the terminal 3 to the metal layer 2, the corner B of the soldering material 5 acts as an adsorbent to prevent excessive melting and adhesion to the external lead terminal 3. . .
尚、前記外部リード端子３、リードフレーム４及びダミ
ーリード６はコバール等の金属板を従来周知の金属打抜
き加工法により打抜くことによって形成される。The external lead terminals 3, lead frame 4, and dummy leads 6 are formed by punching a metal plate such as Kovar using a conventionally known metal punching method.
また前記ロウ材５は銀、銀−銅合金（恨ロウ）、スズ−
鉛合金（半田）等の金属から成り、絶縁基体１の上面に
設けた金属層２上にリードフレーム４に設けた外部リー
ド端子３をロウ付は固着する作用を為す。Further, the brazing material 5 is silver, silver-copper alloy (golden wax), tin-
It is made of a metal such as a lead alloy (solder), and brazing serves to fix the external lead terminals 3 provided on the lead frame 4 onto the metal layer 2 provided on the upper surface of the insulating base 1.
前記ロウ材５は銀−銅合金（銀ロウ）等の金属板を従来
周知の金属打抜き加工法により打抜くことによって方形
環状に形成される。The solder material 5 is formed into a rectangular ring shape by punching a metal plate such as a silver-copper alloy (silver solder) using a conventionally known metal punching method.
次に第２図及び第３図に示すように絶縁基体ｌ、ロウ材
５及びリードフレーム４をカーボンから成る治具（不図
示）内に装填し、絶縁基体１上にロウ材５及びリードフ
レーム４を載置するとともに絶縁基体１に形成した各金
属層２にリードフレーム４に設けた各外部リード端子３
が銀ロウ等のロウ材５を介して正確に対応するよう、ま
たリードフレーム４に設けたダミーリード６がロウ材５
の各隅部Ｂに載置するようロウ材５及びリードフレーム
４の位置決めを行う。Next, as shown in FIGS. 2 and 3, the insulating substrate 1, the brazing material 5, and the lead frame 4 are loaded into a jig (not shown) made of carbon, and the brazing material 5 and the lead frame are placed on the insulating substrate 1. 4 and each external lead terminal 3 provided on the lead frame 4 on each metal layer 2 formed on the insulating base 1.
The dummy leads 6 provided on the lead frame 4 are connected to the soldering material 5 through the soldering material 5 such as silver solder so that the dummy leads 6
The brazing material 5 and the lead frame 4 are positioned so as to be placed on each corner B of the lead frame 4.
かかる位置決めされた絶縁基体１、ロウ材５及びリード
フレーム４は次に約９００℃に加熱された炉中に通され
、絶縁基体１の各金属層２とリードフレーム４に設けた
各外部リード端子３とをその間に配したロウ材５を溶融
させることによってロウ付は固着する。この場合、ロウ
材５の隅部Ｂはダミーリード６に溶融付着し、リードフ
レーム４の各辺に設けた外部リード端子３のうち各通雨
端部に位置するものに溶融付着することはなく、該リー
ドフレームの各通雨端部に位置する外部リード端子にロ
ウ材量の過多によるロウ付は強度の低下が生じることは
ない。The insulating base 1, brazing material 5, and lead frame 4 thus positioned are then passed through a furnace heated to approximately 900°C, and each metal layer 2 of the insulating base 1 and each external lead terminal provided on the lead frame 4 are connected to each other. The brazing is fixed by melting the brazing material 5 with 3 and 3 disposed therebetween. In this case, the corner B of the brazing material 5 melts and adheres to the dummy lead 6, and does not melt and adhere to the external lead terminals 3 provided on each side of the lead frame 4 located at each rain-conducting end. If the external lead terminals located at each rain-conducting end of the lead frame are brazed with an excessive amount of brazing material, the strength will not be reduced.
そして、最後に絶縁基体１の各金属層２にロウ付けされ
た各外部リード端子３を第２図に示す切断線Ｃに沿って
切断し、リードフレーム４を分離除去することよって半
導体素子収納用パフケージが製作される。Finally, each external lead terminal 3 brazed to each metal layer 2 of the insulating substrate 1 is cut along the cutting line C shown in FIG. 2, and the lead frame 4 is separated and removed. A puff cage is made.
尚、この時ダミーリード６もリードフレーム４と同様に
除去される。Incidentally, at this time, the dummy leads 6 are also removed in the same way as the lead frame 4.
本発明の半導体素子収納用パッケージの製造法によれば
、複数個の外部リード端子を有するリードフレームにダ
ミーリードを設け、該ダミーリードを方形環状の口□つ
材の各隅部にｆ２置させるようになしたことから外部リ
ード端子を金属層にロウ付は固着するためにロウ材を加
熱溶融させた際、ロウ材の隅部はダミーリードに溶融付
着して外部リード端子には付着しなくなり、その結果、
すべての外部リード端子と金属層との間に介在する口
′つ材の量をロウ付は強度を大となす所定子とし
て外部リード端子を強固にロウ付は固着することが可能
となる。According to the method of manufacturing a package for storing semiconductor elements of the present invention, dummy leads are provided on a lead frame having a plurality of external lead terminals, and the dummy leads are placed at each corner f2 of a rectangular annular opening member. Because of this, when the brazing material is heated and melted to secure the external lead terminal to the metal layer, the corner of the brazing material melts and adheres to the dummy lead and does not adhere to the external lead terminal. ,the result,
Openings interposed between all external lead terminals and metal layers
By brazing the amount of the material, it becomes possible to firmly fix the external lead terminal by using it as a predetermined element that increases the strength.
第１図は本発明の半通体素子収納用パッケージの製造法
を説明するための分解斜視図、第２図は第１図の半導体
素子収納用パッケージの組立て状態を示す平面図、第３
図は第２図の断面図、第４図は従来の半４体素子の収納
用パッケージの断面図、第５図は第４図のパッケージの
製造法を説明するための分解斜視図である。FIG. 1 is an exploded perspective view for explaining the manufacturing method of the package for housing a semi-through element of the present invention, FIG. 2 is a plan view showing the assembled state of the package for housing a semiconductor element in FIG. 1, and FIG.
The figures are a cross-sectional view of FIG. 2, FIG. 4 is a cross-sectional view of a conventional package for housing a half-quad element, and FIG. 5 is an exploded perspective view for explaining a method of manufacturing the package of FIG. 4.
Claims (1)
面もしくは下面の周縁部に複数個の金属層が被着形成さ
れた方形状の絶縁容器を準備し、複数個の外部リード端
子及びダミーリードを備えたリードフレームを方形環状
のロウ材を介して前記絶縁容器上に載置し、各外部リー
ド端子をこれに対応する各金属層に、またダミーリード
を方形状環状のロウ材の各隅部に位置合わせし、次いで
、前記ロウ材を加熱溶融させ、各外部リード端子をそれ
に対応する各金属層上に固着し、その後、前記各外部リ
ード端子をリードフレームより切断し、該リードフレー
ムを除去する ことを特徴とする半導体素子収納用パッケージの製造法
。[Claims] A rectangular insulating container having a cavity for accommodating a semiconductor element therein and having a plurality of metal layers deposited on the periphery of the upper or lower surface is prepared, A lead frame equipped with external lead terminals and dummy leads is placed on the insulating container via a rectangular ring-shaped brazing material, and each external lead terminal is connected to each metal layer corresponding to the lead frame, and the dummy lead is connected to the corresponding metal layer. Each corner of the annular brazing material is aligned, and then the brazing material is heated and melted to fix each external lead terminal onto the corresponding metal layer. Thereafter, each external lead terminal is attached to a lead frame. A method for manufacturing a package for housing a semiconductor element, comprising cutting the lead frame further and removing the lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61166464A JPH0789577B2 (en) | 1986-07-14 | 1986-07-14 | Manufacturing method of package for storing semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61166464A JPH0789577B2 (en) | 1986-07-14 | 1986-07-14 | Manufacturing method of package for storing semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6320858A true JPS6320858A (en) | 1988-01-28 |
| JPH0789577B2 JPH0789577B2 (en) | 1995-09-27 |
Family
ID=15831882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61166464A Expired - Lifetime JPH0789577B2 (en) | 1986-07-14 | 1986-07-14 | Manufacturing method of package for storing semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0789577B2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58188142A (en) * | 1982-04-28 | 1983-11-02 | Hitachi Ltd | Ceramic substrate |
| JPS59139658A (en) * | 1983-12-02 | 1984-08-10 | Hitachi Ltd | Electronic circuit device |
| JPS59141256A (en) * | 1983-02-02 | 1984-08-13 | Hitachi Ltd | Brazing method of lead frame |
-
1986
- 1986-07-14 JP JP61166464A patent/JPH0789577B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58188142A (en) * | 1982-04-28 | 1983-11-02 | Hitachi Ltd | Ceramic substrate |
| JPS59141256A (en) * | 1983-02-02 | 1984-08-13 | Hitachi Ltd | Brazing method of lead frame |
| JPS59139658A (en) * | 1983-12-02 | 1984-08-10 | Hitachi Ltd | Electronic circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0789577B2 (en) | 1995-09-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |